Li / Chen Nonvolatile Memory Design

Magnetic, Resistive, and Phase Change
1. Auflage 2011
ISBN: 978-1-4398-0746-0
Verlag: CRC Press
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 208 Seiten

The manufacture of flash memory, which is the dominant nonvolatile memory technology, is facing severe technical barriers. So much so, that some emerging technologies have been proposed as alternatives to flash memory in the nano-regime. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing introduces three promising candidates: phase-change memory, magnetic random access memory, and resistive random access memory. The text illustrates the fundamental storage mechanism of these technologies and examines their differences from flash memory techniques. Based on the latest advances, the authors discuss key design methodologies as well as the various functions and capabilities of the three nonvolatile memory technologies.

Zielgruppe

Senior undergraduate students/graduate students in electrical engineering, VLSI, microelectronic, semiconductor and materials; engineers working with nonvolatile memory products, design house/foundry that supplies nonvolatile memory IP, or working at a microprocessor/microcontroller that has on-chip embedded (nonvolatile) memory; researchers working on nonvolatile storage devices.

Autoren/Hrsg.

Li, Hai

Chen, Yiran

Fachgebiete

• Technische Wissenschaften Maschinenbau | Werkstoffkunde Technische Mechanik | Werkstoffkunde Materialwissenschaft: Elektronik, Optik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Schaltungsentwurf
• Mathematik | Informatik EDV | Informatik Technische Informatik Hardware: Grundlagen und Allgemeines
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Halb- und Supraleitertechnologie

Inhaltsverzeichnis

1 Introduction to Semiconductor Memories
1.1 Classification and Characterization of Semiconductor Memories
1.1.1 Read-Only Memories (ROMs)
1.1.2 Static Random Access Memories (SRAMs)
1.1.3 Dynamic Random Access Memories (DRAMs)
1.1.4 Non-Volatile Memories
1.1.5 Embedded Memories Design and Applications
1.2 The Devices
1.2.1 The Diode
1.2.2 The MOS(FET) Transistor
1.2.3 Passive Components
1.3 Designing Memory and Array Structures
1.3.1 Memory Architecture and Building Blocks
1.3.2 Memory Peripheral Circuitry
1.3.3 Redundancy and Error Correction Codes
1.3.4 Test Modes
1.3.5 Memory Reliability and Yield
References
2 Phase Change Memory (PCM)
2. 1 Introduction of PCM
2.1.1 Phase Change Properties
2.1.2 History of PCM
2.2 Device Research
2.2.1 Bridge Cell
2.2.2 Pillar Cell
2.2.3 Pore Cell
2.2.4 Electro-thermal Modeling
2.3 Material Research
2.3.1 Ge2Sb2Te5 Alloys
2.3.2 N-Doped GST
2.3.3 Other Phase Change Materials
2.4 PCM Design Technique
2.4.1 Reset/Set Characteristics
2.4.2 Access device of PCM Bit Cell
2.4.3 Multi-level Cell
2.4.4 Program Algorithm
2.4.5 Peripheral Circuitry
2.5 Physical Limit of PCM
2.5.1 Bit Retention
2.5.2 Bit Endurance
2.5.3 Continue Moore's law
References
3 Toggle-Mode MRAM (TM-MRAM)
3. 1 Overview of Magnetic Memories
3.2 Magnetic Tunneling Junction (MTJ) Technology
3.2.1 Basic Structure of MT J Stack
3.2.2 Conventional MT J Switching
3.3 Operation of Toggle-Mode
3.3.1 Savtchenko Switching
3.3.2 Reading from an Array
3.4 Manufacture Technology of TM-MRAM Bit Cell
3.4.1 MT J Deposition
3.4.2 BEOL and FEOL of TM-MRAM Bit Cell
3.4.3 Resistance Variation Control within Array
3.4.4 Barrier Uniformity Control
3.4.5 Interface Quality Control
3.5 Design Technique of TM-MRAM
3.5.1 Bit Selection from Array
3.5.2 Bit Resistance Distribution and Read Scheme
3.5.3 Toggle Switching Circuitry
3.5.4 Failures Mode, Redundancy and ECC
3.6 Reliability, Endurance and Scalability
3.6.1 Bit Disturb Margin
3.6.2 Thermal Reliability
3.6.3 Magnetic Stability
3.6.4 Endurance and Retention
3.6.5 Scalability at 130nm Technology and Beyond
References
4 Spin-Torque Transfer RAM (STT -RAM)
4.1 Introduction of Spin-Torque Transfer technology
4.1.1 Spin-Torque Transfer Theory
4.1.2 Various STT -RAM Bit Cell Designs
4.2 Read and Write Scheme of STT-RAM
4.2.1 Magnetic Modeling
4.2.2 Switching Current Variation
4.2.3 Tunneling Magnetoresistance (TMR) and Sense Margin
4.3 Variations of STT-RAM Bit Cell
4.3.1 Sources of Switching Current Variation
4.3.2 Sources of MT J Resistance Variation
4.3.3 MOS Transistor Process Variation
4.3.4 Variation Control of STT -RAM Bit Cell
4.4 Design Technique of STT-RAM
4.4.1 STT -RAM Cell Design
4.4.2 Write Scheme Optimization for High Density
4.4.3 Reference and Sensing Scheme
4.4.4 Layout optimization
4.4.5 Peripheral Circuitry
4.4.6 Design for Embedded Application
4.5 Failure Modes in STT-RAM
4.5.1 Static Failure Modes
4.5.2 Random Failure Modes
4.5.3 Failures due to Process Variation
4.5.4 Failure Repair
4.6 Applications and Technology Trends of STT-RAM
4.6.1 Potential applications
4.6.2 Product Roadmap
4.6.3 Future Research
References
5 Resistive RAM (R-RAM)
5. 1 Overview of R-RAM
5.1.1 Definition of R-RAM
5.1.2 Operation Schemes
5.2 Various Switching Mechanisms of R-RAM
5.2.1 Resistance Switching Models
5.2.2 Space Charge Limited Current
5.2.3 Filament
5.2.4 Programmable Metallization Cell (PMC)
5.2.5 Schottky Contact and Traps
5.2.6 Miscellaneous
5.3 R-RAM Design
5.3.1 Multi-level Cell (MLC)
5.3.2 Forming, Set/Reset Scheme
5.3.3 4F2 Cell
5.3.4 Unipolar and Bipolar Writing
5.3.5 Cross Point Memory Array
5.3.6 Special Circuitry for R-RAM
5.4 Technology Trend and Application of R-RAM
5.4.1 Endurance and Retention
5.4.2 Scalability
5.4.3 Material Challenges
5.4.4 Massive Storage based on R-RAM
References
6 Memresistor
6. 1 Fourth Passive Circuit Element - Memresistor
6.1.1 History of Memresistor
6.1.2 Theory of Memresistor
6.2 R-RAM-like Memresistor
6.2.1 Titanium Dioxide as Memresistor
6.2.2 Other Options
6.3 Magnetic Memresistor
6.3.1 Spintronics Device as Memresistor
6.3.2 I-V Curve and Frequency Response
6.4 Applications and Future Trends
6.4.1 Memresistor Memory
6.4.2 Memresistor Logic
References
7 The Future of Nonvolatile Memory
7. 1 Development Progress of Future Nonvolatile Memory Technologies
7.1.1 Review of current efforts in the world
7.1.2 Future research trend
7.2 Who will be the winner?
7.2.1 Semiconductor Memory Roadmap
7.2.2 Forecast
References