Zhao / Dai Low-Noise Low-Power Design for Phase-Locked Loops

Multi-Phase High-Performance Oscillators
2015
ISBN: 978-3-319-12200-7
Verlag: Springer International Publishing
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 96 Seiten, eBook

This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation.  The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage.  Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.

Zielgruppe

Research

Autoren/Hrsg.

Zhao, Feng

Dai, Fa Foster

Inhaltsverzeichnis

Introduction.- Analysis of Quantization Noise Reduction Techniques for Fractional-N PLL.- A Wide-Band 0.13µm SiGe BiCMOS PLL for X-Band Radar.- Design and Analysis of QVCO with Different Coupling Techniques.- Design and Analysis of a 0.6V QVCO with Capacitive-Coupling Technique.- Conclusions.