Zhang High-speed Serial Buses in Embedded Systems

1. Auflage 2020
ISBN: 978-981-15-1868-3
Verlag: Springer Nature Singapore
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 373 Seiten

This book describes the most frequently used high-speed serial buses in embedded systems, especially those used by FPGAs. These buses employ SerDes, JESD204, SRIO, PCIE, Aurora and SATA protocols for chip-to-chip and board-to-board communication, and CPCIE, VPX, FC and Infiniband protocols for inter-chassis communication. For each type, the book provides the bus history and version info, while also assessing its advantages and limitations. Furthermore, it offers a detailed guide to implementing these buses in FPGA design, from the physical layer and link synchronization to the frame format and application command. Given its scope, the book offers a valuable resource for researchers, R&D engineers and graduate students in computer science or electronics who wish to learn the protocol principles, structures and applications of high-speed serial buses.

Dr. Zhang Feng is a Senior Engineer. His research areas include data recording systems such as CCD, SATA, SRIO, FC and CPCIE, as well as the design of embedded systems used in wireless communication, including SerDes, JESD204, Aurora, and VPX.

Autoren/Hrsg.

Zhang, Feng

Inhaltsverzeichnis

1;Preface;5
1.1;What This Book Is About?;5
1.2;Why the Serial Buses?;6
1.3;Who Is This Book For?;6
1.4;Outline of This Book;6
2;Contents;7
3;1 History and Development of Bus;13
3.1;1.1 Appearance and Definition of Bus;13
3.2;1.2 Progress of Bus in PC;15
3.2.1;1.2.1 ISA;16
3.2.2;1.2.2 PCI/PCI-X;17
3.2.3;1.2.3 PCIE;20
3.2.4;1.2.4 ATA/SATA—Used for Storage;22
3.3;1.3 Progress of Bus in Embedded System;24
3.3.1;1.3.1 The Emergence of Embedded Systems;24
3.3.2;1.3.2 PC104—The Embedded Version of ISA;26
3.3.3;1.3.3 Compact PCI—The Embedded Version of PCI;28
3.3.4;1.3.4 Compact PCI Express—The Embedded Version of PCI Express;31
3.3.5;1.3.5 SRIO—The Embedded System Interconnection;32
3.3.6;1.3.6 JESD204—Solving the ADC, DAC Data Transfer Problem;35
3.3.7;1.3.7 FC—A Combination of Channel I/O and Network I/O;36
3.3.8;1.3.8 VPX—An Integration Architecture of High-Speed Serial Bus;38
3.4;1.4 Analysis of the Three Evolutions of Bus;39
3.5;1.5 Common Attributes in High-Speed Serial Buses;43
3.6;1.6 The Development Trend of High-Speed Serial Bus in Embedded System;45
3.6.1;1.6.1 Speed Upgrades Constantly;46
3.6.2;1.6.2 Adoption of Multiple Signal Levels;46
3.6.3;1.6.3 Laser Communication and Its Miniaturization;47
3.6.4;1.6.4 Extended Reading—Laser Takes the Place of Microwave Communication [36];49
3.7;References;51
4;2 High-Speed Data Transfer Based on SERDES;53
4.1;2.1 Brief Introduction to Serdes;53
4.2;2.2 LVDS—Physical Layer of Serdes;54
4.3;2.3 Data Transfer Based on Serdes Primitive Embedded in FPGA;57
4.3.1;2.3.1 FPGA Supports LVDS Level;57
4.3.2;2.3.2 FPGA Embeds-in OSERDESE2/ISERDESE2 Primitives;58
4.3.3;2.3.3 Analysis of the Transfer Rate of Serdes;60
4.4;2.4 Implementation of Serdes Transfer Function in FPGA;61
4.4.1;2.4.1 OSERDESE2 Configuration at the Transmitter in FPGA;61
4.4.2;2.4.2 ISERDESE2 Design at the Receiver in FPGA;74
4.4.3;2.4.3 Experiment Result of Serdes Communication;82
4.5;2.5 Extended Reading—Optimization Scheme for Multi-channel Communication Based on Serdes;83
4.5.1;2.5.1 Clock Region Optimization;84
4.5.2;2.5.2 MAXSKEW;85
4.5.3;2.5.3 Offset;87
4.5.4;2.5.4 IDELAY2 Primitives to Adjust the Delay;89
4.5.5;2.5.5 A Self-Adaptive Delay Adjustment Scheme Based on Idelay2 Primitive;92
4.6;2.6 Brief Summary;93
4.7;2.7 Extended Reading—A New Rising Star: Xilinx and Its FPGA;94
4.8;References;95
5;3 ADC, DAC Data Transmission Based on JESD204 Protocol;97
5.1;3.1 Introduction to JESD204 Protocol;97
5.2;3.2 Detailed Analysis of JESD204 Specification;102
5.2.1;3.2.1 JESD204 Physical Layer Analysis;102
5.2.2;3.2.2 Frame Padding;104
5.2.3;3.2.3 8B/10B;105
5.2.4;3.2.4 Scrambling/De-scrambling;108
5.2.5;3.2.5 Analysis of JESD204 Protocol Receiver State Machine;109
5.3;3.3 Implementation of JESD204 Protocol Based on GTX Embedded in FPGA;112
5.3.1;3.3.1 Feasibility Analysis—Physical Layer Electrical Characteristics Compatibility;113
5.3.2;3.3.2 GTX Structure Analysis;113
5.3.3;3.3.3 Build the FPGA Project for JESD204 IP Core Based on GTX;121
5.3.4;3.3.4 Analysis of Some Technical Points of JESD204 Protocol;135
5.4;3.4 Summary;140
5.5;References;141
6;4 SRIO: The Embedded System Interconnection;143
6.1;4.1 SRIO—Dedicated for the Embedded System Interconnection;143
6.1.1;4.1.1 Embedded Bus and PC Bus Applications Went Separate Ways;143
6.1.2;4.1.2 SRIO Technology Dedicated for Embedded System Interconnection;145
6.1.3;4.1.3 SRIO Versus PCIE Versus Ethernet Versus Others;147
6.2;4.2 SRIO Protocol Analysis;149
6.2.1;4.2.1 SRIO Protocol Hierarchical Structure;149
6.2.2;4.2.2 SRIO Physical Layer Specification;152
6.2.3;4.2.3 Packet and Operation Types;155
6.2.4;4.2.4 Lane Synchronization;158
6.2.5;4.2.5 Lane Encoding;158
6.2.6;4.2.6 Configuration Space;161
6.3;4.3 Point to Point SRIO Communication Based on FPGA;161
6.3.1;4.3.1 Create the SRIO Project;163
6.3.2;4.3.2 SRIO Project Structure Analysis [7];174
6.3.3;4.3.3 Analysis and Realization of Key Technology of SRIO Point-to-Point Communication;176
6.3.4;4.3.4 SRIO P2P Communication Function Test;179
6.4;4.4 The Implementation of Communication Function of SRIO Switch Fabric;180
6.4.1;4.4.1 Overview of the SRIO Switch Fabric;180
6.4.2;4.4.2 Brief Introduction on SRIO Switch Chip 80HCPS1616 [8, 9];181
6.4.3;4.4.3 The Configuration of SRIO Switch Chip 80HCPS1616;183
6.4.4;4.4.4 I2C Configuration Interface for 80HCPS1616;190
6.4.5;4.4.5 Maintenance Frame Configuration for SRIO Switch Chip;192
6.4.6;4.4.6 Communication Function Test of SRIO Switch Fabric;198
6.5;4.5 Summary;199
6.6;References;201
7;5 Transmission Technology Based on Aurora Protocol;202
7.1;5.1 Aurora Bus Overview;202
7.2;5.2 Aurora Bus Protocol Analysis;203
7.2.1;5.2.1 Aurora Bus Communication Model;203
7.2.2;5.2.2 Electrical Characteristics of Aurora Physical Layer;204
7.2.3;5.2.3 Aurora Data Frame Structure;206
7.2.4;5.2.4 Aurora Lane Synchronization;208
7.3;5.3 Implementation of Aurora Point-to-Point Data Transmisstion Between FPGAs;212
7.3.1;5.3.1 Establish Aurora Bus Testing Project;212
7.3.2;5.3.2 Analysis of Aurora Bus Protocol Files and Interfaces;218
7.3.3;5.3.3 Aurora Bus Frame Mode and Streaming Mode;220
7.3.4;5.3.4 Aurora Bus Communication Performance Analysis and Test;225
7.4;5.4 Summary;228
7.5;References;228
8;6 High Speed Data Storage Technology Based on SATA;229
8.1;6.1 Various Modes of High-Speed Data Storage Technology and the Involved Buses;230
8.1.1;6.1.1 Data Storage Mode Based on ATA Bus Standard;230
8.1.2;6.1.2 High Speed Data Storage Mode Based on SCSI Bus Standard;232
8.1.3;6.1.3 High Speed Data Storage Mode Based on SAS/SATA Bus Standard;234
8.1.4;6.1.4 Extended Reading—High Speed Data Storage Mode Based on NandFlash Arrays;237
8.1.5;6.1.5 Extended Reading—High Speed Data Storage Mode Based on eMMCs and Its Array;240
8.1.6;6.1.6 Comparison and Analysis of Multiple Storage Implementations;241
8.2;6.2 SATA Protocol Analysis;242
8.2.1;6.2.1 Architecture;242
8.2.2;6.2.2 OOB Process;243
8.2.3;6.2.3 Primitives and Frame Information Structures;245
8.2.4;6.2.4 Encode Scheme;250
8.3;6.3 Implementation of SATA IP Core in FPGA;250
8.3.1;6.3.1 Brief Introduction to ML50x Evaluation Platforms [15];251
8.3.2;6.3.2 Brief Introduction to Virtex-5 FPGA GTX [16];251
8.3.3;6.3.3 GTX Configurations to Comply with SATA Protocol;254
8.3.4;6.3.4 OOB Communication of SATA Protocol;262
8.3.5;6.3.5 Implementation of 8B/10B, CRC and Scrambling;265
8.3.6;6.3.6 Implementation of Analysis on Application Layer of SATA Protocol;267
8.3.7;6.3.7 Implementation of Application Layer;273
8.3.8;6.3.8 SATA Protocol IP CoreTest;274
8.4;6.4 Summary;276
8.5;6.5 Extended Reading—DNA-Based Biology Storage Technology;277
8.6;Appendix 1: SATA CRC32 Implementation in VHDL;283
8.7;Appendix 2: SATA Scrambling Implementation in VHDL;290
8.8;References;296
9;7 Compact PCI Express;298
9.1;7.1 From ISA to PCI to PCIE;298
9.2;7.2 Compact PCIE—Embedded Version of PCIE;304
9.3;7.3 Classification of Functional Modules in CPCIE;306
9.4;7.4 CPCIE Connectors and Signals Definition;308
9.4.1;7.4.1 Connectors;308
9.4.2;7.4.2 Definition of Signals;310
9.5;7.5 System Design Considerations;321
9.5.1;7.5.1 Functional Labels of Boards;321
9.5.2;7.5.2 Power Supply Requirements;323
9.5.3;7.5.3 Clock Design;325
9.6;7.6 Summary;325
9.7;References;326
10;8 VPX Architecture;327
10.1;8.1 Brief Introduction to VPX and Its Origin VME;327
10.2;8.2 Analysis on VPX Protocol Families;331
10.3;8.3 Signals and Interconnect;335
10.3.1;8.3.1 VME32 Signals;335
10.3.2;8.3.2 VPX Signals;337
10.3.3;8.3.3 Pin Mappings Between Backplane and Plug-in Modules;337
10.4;8.4 System Design Consideration;337
10.4.1;8.4.1 Logical Topology;337
10.4.2;8.4.2 Connectors Selection;340
10.4.3;8.4.3 Backplane Keying;341
10.4.4;8.4.4 Power Design;343
10.5;8.5 Summary;348
10.6;References;349
11;9 Implementation and Application of FC Protocol;350
11.1;9.1 Brief Introduction to FC;350
11.1.1;9.1.1 FC Appears from Big Data, Clouds and SAN;350
11.1.2;9.1.2 Advantages of FC;352
11.1.3;9.1.3 FC Roadmap;353
11.1.4;9.1.4 Applications of FC to Airborne Avionics;354
11.2;9.2 Analysis of FC Specification;355
11.2.1;9.2.1 FC Topology;355
11.2.2;9.2.2 Hierarchical-Layered Structure;357
11.2.3;9.2.3 FC Protocol Families;359
11.2.4;9.2.4 Frame Structure and Coding Scheme;359
11.2.5;9.2.5 Classes of Service;363
11.2.6;9.2.6 Interface Forms;368
11.3;9.3 Analysis on Realization of FC Protocols;368
11.3.1;9.3.1 Realization Scheme Based on IP of Xilinx;369
11.3.2;9.3.2 Realization Method Based on ASICs;370
11.4;9.4 Summary;372
11.5;References;373