Yiu The Definitive Guide to the ARM Cortex-M0

1. Auflage 2011
ISBN: 978-0-12-385478-0
Verlag: Elsevier Science & Techn.
Format: EPUB
Kopierschutz: 6 - ePub Watermark

E-Book, Englisch, 552 Seiten

The Definitive Guide to the ARM Cortex-M0 is a guide for users of ARM Cortex-M0 microcontrollers. It presents many examples to make it easy for novice embedded-software developers to use the full 32-bit ARM Cortex-M0 processor. It provides an overview of ARM and ARM processors and discusses the benefits of ARM Cortex-M0 over 8-bit or 16-bit devices in terms of energy efficiency, code density, and ease of use, as well as their features and applications. The book describes the architecture of the Cortex-M0 processor and the programmers model, as well as Cortex-M0 programming and instruction set and how these instructions are used to carry out various operations. Furthermore, it considers how the memory architecture of the Cortex-M0 processor affects software development; Nested Vectored Interrupt Controller (NVIC) and the features it supports, including flexible interrupt management, nested interrupt support, vectored exception entry, and interrupt masking; and Cortex-M0 features that target the embedded operating system. It also explains how to develop simple applications on the Cortex-M0, how to program the Cortex-M0 microcontrollers in assembly and mixed-assembly languages, and how the low-power features of the Cortex-M0 processor are used in programming. Finally, it describes a number of ARM Cortex-M0 products, such as microcontrollers, development boards, starter kits, and development suites. This book will be useful to both new and advanced users of ARM Cortex devices, from students and hobbyists to researchers, professional embedded- software developers, electronic enthusiasts, and even semiconductor product designers. - The first and definitive book on the new ARM Cortex-M0 architecture targeting the large 8-bit and 16-bit microcontroller market - Explains the Cortex-M0 architecture and how to program it using practical examples - Written by an engineer at ARM who was heavily involved in its development

Joseph Yiu joined Arm in 2001 and has been involved in a wide range of projects including development of Arm Cortex-M processors and various on-chip system level and debug components. In addition to in-depth knowledge of the processors and microcontroller system design, Joseph also has extensive knowledge in related areas including software development for the Arm Cortex-M microcontrollers, FPGA development and System-on-Chip design technologies.

Autoren/Hrsg.

Yiu, Joseph

Leseproben

Chapter 2. Cortex-M0 Technical Overview

General Information on the Cortex-M0 Processor

The Cortex-M0 processor is a 32-bit Reduced Instruction Set Computing (RISC) processor with a von Neumann architecture (single bus interface). It uses an instruction set called Thumb, which was first supported in the ARM7TDMI processor; however, several newer instructions from the ARMv6 architecture and a few instructions from the Thumb-2 technology are also included. Thumb-2 technology extended the previous Thumb instruction set to allow all operations to be carried out in one CPU state. The instruction set in Thumb-2 included both 16-bit and 32-bit instructions; most instructions generated by the C compiler use the 16-bit instructions, and the 32-bit instructions are used when the 16-bit version cannot carry out the required operations. This results in high code density and avoids the overhead of switching between two instruction sets.

In total, the Cortex-M0 processor supports only 56 base instructions, although some instructions can have more than one form. Although the instruction set is small, the Cortex-M0 processor is highly capable because the Thumb instruction set is highly optimized. Academically, the Cortex-M0 processor is classified as load-store architecture, as it has separate instructions for reading and writing to memory, and instructions for arithmetic or logical operations that use registers.

A simplified block diagram of the Cortex-M0 is shown in Figure 2.1.

Figure 2.1 Simplified block diagram of the Cortex-M0 processor.

The processor core contains the register banks, ALU, data path, and control logic. It is a three-stage pipeline design with fetch stage, decode stage, and execution stage. The register bank has sixteen 32-bit registers. A few registers have special usages.

The Nested Vectored Interrupt Controller (NVIC) accepts up to 32 interrupt request signals and a nonmaskable interrupt (NMI) input. It contains the functionality required for comparing priority between interrupt requests and the current priority level so that nested interrupts can be handled automatically. If an interrupt is accepted, it communicates with the processor so that the processor can execute the correct interrupt handler.

The Wakeup Interrupt Controller (WIC) is an optional unit. In low-power applications, the microcontroller can enter standby state with most of the processor powered down. In this situation, the WIC can perform the function of interrupt masking while the NVIC and the processor core are inactive. When an interrupt request is detected, the WIC informs the power management to power up the system so that the NVIC and the processor core can then handle the rest of the interrupt processing.

The debug subsystem contains various functional blocks to handle debug control, program breakpoints, and data watchpoints. When a debug event occurs, it can put the processor core in a halted state so that embedded developers can examine the status of the processor at that point.

The JTAG or serial wire interface units provide access to the bus system and debugging functionalities. The JTAG protocol is a popular five-pin communication protocol commonly used for testing. The serial wire protocol is a newer communication protocol that only requires two wires, but it can handle the same debug functionalities as JTAG.

The internal bus system, the data path in the processor core, and the AHB LITE bus interface are all 32 bits wide. AHB-Lite is an on-chip bus protocol used in many ARM processors. This bus protocol is part of the Advanced Microcontroller Bus Architecture (AMBA) specification, a bus architecture developed by ARM that is widely used in the IC design industry.

The ARM Cortex-M0 Processor Features

The ARM Cortex-M0 processor contains many features. Some are visible system features, and others are not visible to embedded developers.

System Features

• Thumb instruction set. Highly efficient, high code density and able to execute all Thumb instructions from the ARM7TDMI processor.

• High performance. Up to 0.9 DMIPS/MHz (Dhrystone 2.1) with fast multiplier or 0.85 DMIPS/MHz with smaller multiplier.

• Built-in Nested Vectored Interrupt Controller (NVIC). This makes interrupt configuration and coding of exception handlers easy. When an interrupt request is taken, the corresponding interrupt handler is executed automatically without the need to determine the exception vector in software.

• Interrupts can have four different programmable priority levels. The NVIC automatically handles nested interrupts.

• Deterministic exception response timing. The design can be set up to respond to exceptions (e.g., interrupts) with a fixed number of cycles (constant interrupt latency arrangement) or to respond to the exception as soon as possible (minimum 16 clock cycles).

• Nonmaskable interrupt (NMI) input for safety critical systems.

• Architectural predefined memory map. The memory space of the Cortex-M0 processor is architecturally predefined to make software porting easier and to allow easier optimization of chip design. However, the arrangement is very flexible. The memory space is linear and there is no memory paging required like in a number of other processor architectures.

• Easy to use and C friendly. There are only two modes (Thread mode and Handler mode). The whole application, including exception handlers, can be written in C without any assembler.

• Built-in optional System Tick timer for OS support. A 24-bit timer with a dedicated exception type is included in the architecture, which the OS can use as a tick timer or as a general timer in other applications without an OS.

• SuperVisor Call (SVC) instruction with a dedicated SVC exception and PendSV (Pendable Supervisor service) to support various operations in an embedded OS.

• Architecturally defined sleep modes and instructions to enter sleep. The sleep features allow power consumption to be reduced dramatically. Defining sleep modes as an architectural feature makes porting of software easier because sleep is entered by a specific instruction rather than implementation defined control registers.

• Fault handling exception to catch various sources of errors in the system.

Implementation Features

• Configurable number of interrupts (1 to 32)

• Fast multiplier (single cycle) or small multiplier (for a smaller chip area and lower power, 32 cycles)

• Little endian or big endian memory support

• Optional Wakeup Interrupt Controller (WIC) to allow the processor to be powered down during sleep, while still allowing interrupt sources to wake up the system

• Very low gate count, which allows the design to be implemented in mixed signal semiconductor processes

Debug Features

• Halt mode debug. Allows the processor activity to stop completely so that register values can be accessed and modified. No overhead in code size and stack memory size.

• CoreSight technology. Allows memories and peripherals to be accessed from the debugger without halting the processor. It also allows a system-on-chip design with multiple processors to share a single debug connection.

• Supports JTAG connection and serial wire debug connections. The serial wire debug protocol can handle the same debug features as the JTAG, but it only requires two wires and is already supported by a number of debug solutions from various tools vendors.

• Configurable number of hardware breakpoints (from 0 to maximum of 4) and watchpoints (from 0 to maximum of 2). The chip manufacturer defines this during implementation.

• Breakpoint instruction support for an unlimited number of software breakpoints.

• All debug features can be omitted by chip vendors to allow minimum size implementations.

Others

• Programmer’s model similar to the ARM7TDMI processor. Most existing Thumb code for the ARM7TDMI processor can be reused. This also makes it easy for ARM7TDMI users, as there is no need to learn a new instruction set.

• Compatible with the Cortex-M1 processor. This allows users of the Cortex-M1 processor to migrate their FPGA designs to an ASICs easily.

• Forward compatibility with the ARM Cortex-M3 and Cortex-M4 processors. All instructions supported in the Cortex-M0 processor are supported on the Cortex-M3 processor, which allows an easy upgrade path.

• Easy porting from the ARM Cortex-M3/M4. Because of the similarities between the architectures, many C applications for the Cortex-M3/M4 can be ported to the Cortex-M0 processor easily. This is great news for middleware vendors and embedded OS vendors, as it is straightforward to port their existing software products for Cortex-M3 microcontrollers to Cortex-M0 microcontrollers.

• Supported by various development suites including the ARM Keil Microcontroller Development Kit (MDK), the ARM RealView Development Suite (RVDS), the IAR C compiler, and the open source GNU C compiler, including tool chains based on gcc (e.g.,...