Buch, Englisch, Band 4943, 346 Seiten, Format (B × H): 155 mm x 235 mm, Gewicht: 546 g
4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings
Buch, Englisch, Band 4943, 346 Seiten, Format (B × H): 155 mm x 235 mm, Gewicht: 546 g
Reihe: Lecture Notes in Computer Science
ISBN: 978-3-540-78609-2
Verlag: Springer Berlin Heidelberg
Zielgruppe
Research
Autoren/Hrsg.
Fachgebiete
- Mathematik | Informatik EDV | Informatik Technische Informatik Netzwerk-Hardware
- Mathematik | Informatik EDV | Informatik Informatik
- Mathematik | Informatik EDV | Informatik Technische Informatik Externe Speicher & Peripheriegeräte
- Mathematik | Informatik EDV | Informatik Programmierung | Softwareentwicklung Spiele-Programmierung, Rendering, Animation
- Mathematik | Informatik EDV | Informatik Programmierung | Softwareentwicklung Grafikprogrammierung
- Mathematik | Informatik EDV | Informatik Technische Informatik Hochleistungsrechnen, Supercomputer
- Mathematik | Informatik EDV | Informatik Technische Informatik Systemverwaltung & Management
- Mathematik | Informatik EDV | Informatik Technische Informatik Hardware: Grundlagen und Allgemeines
Weitere Infos & Material
Keynotes.- Synthesizing FPGA Circuits from Parallel Programs.- From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing.- The von Neumann Syndrome and the CS Education Dilemma.- Programming and Compilation.- Optimal Unroll Factor for Reconfigurable Architectures.- Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systems.- DNA and String Processing Applications.- DNA Physical Mapping on a Reconfigurable Platform.- Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension.- Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs.- Scientific Applications.- A Custom Processor for a TDMA Solver in a CFD Application.- A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation.- Reconfigurable Computing Hardware and Systems.- Physical Design of FPGA Interconnect to Prevent Information Leakage.- Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs.- Run-Time Adaptable Architectures for Heterogeneous Behavior Embedded Systems.- Image Processing.- FPGA-Based Real-Time Super-Resolution on an Adaptive Image Sensor.- A Parallel Hardware Architecture for Image Feature Detection.- Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System.- Run-Time Behavior.- A New Self-managing Hardware Design Approach for FPGA-Based Reconfigurable Systems.- A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor.- Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens.- Instruction Set Extension.- ARISE Machines: Extending Processors with Hybrid Accelerators.- The Instruction-Set Extension Problem: A Survey.- Random Number Generation and Financial Computation.- An FPGA Run-Time Parameterisable Log-Normal Random Number Generator.- Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA.- Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models.- Posters.- Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.- Multiplier-Based Double Precision Floating Point Divider According to the IEEE-754 Standard.- Creating the World’s Largest Reconfigurable Supercomputing System Based on the Scalable SGI® Altix® 4700 System Infrastructure and Benchmarking Life-Science Applications.- Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs.- A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures.- PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications.- Stream Transfer Balancing Scheme Utilizing Multi-path Routing in Networks on Chip.- Efficiency of Dynamic Reconfigurable Datapath Extensions – A Case Study.- Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices.- Data Reallocation by Exploiting FPGA Configuration Mechanisms.- A Networked, Lightweight and Partially Reconfigurable Platform.- Neuromolecularware – A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis.- An FPGA Configuration Scheme for Bitstream Protection.- Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture.
