Buch, Englisch, 306 Seiten, Format (B × H): 160 mm x 241 mm, Gewicht: 1440 g
ISBN: 978-0-7923-9472-3
Verlag: Springer US
is intended for both design engineers who want to use VHDL-based logic synthesis ASICs and for managers who need to gain a practical understanding of the issues involved in using this technology. The emphasis is placed more on practical applications of VHDL and synthesis based on actual experiences, rather than on a more theoretical approach to the language.
VHDL and logic synthesis tools provide very powerful capabilities for ASIC design, but are also very complex and represent a radical departure from traditional design methods. This situation has made it difficult to get started in using this technology for both designers and management, since a major learning effort and `culture' change is required. has been written to help design engineers and other professionals successfully make the transition to a design methodology based on VHDL and log synthesis instead of the more traditional schematic based approach. While there are a number of texts on the VHDL language and its use in simulation, little has been written from a designer's viewpoint on how to use VHDL and logic synthesis to design real ASIC systems. The material in this book is based on experience gained in successfully using these techniques for ASIC design and relies heavily on realistic examples to demonstrate the principles involved.
VHDL and logic synthesis tools provide very powerful capabilities for ASIC design, but are also very complex and represent a radical departure from traditional design methods. This situation has made it difficult to get started in using this technology for both designers and management, since a major learning effort and `culture' change is required. has been written to help design engineers and other professionals successfully make the transition to a design methodology based on VHDL and log synthesis instead of the more traditional schematic based approach. While there are a number of texts on the VHDL language and its use in simulation, little has been written from a designer's viewpoint on how to use VHDL and logic synthesis to design real ASIC systems. The material in this book is based on experience gained in successfully using these techniques for ASIC design and relies heavily on realistic examples to demonstrate the principles involved.
Wilderotter / Ott
A Designer's Guide to VHDL Synthesis jetzt bestellen!
Zielgruppe
Research
Autoren/Hrsg.
Fachgebiete
- Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Schaltungsentwurf
- Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
- Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
- Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
Weitere Infos & Material
Preface. 1. Introduction. 2. Making the Transition to VHDL Synthesis. 3. VHDL Background for Synthesis. 4. Synthesis of Sequential Circuits. 5. Sequential Counter Applications. 6. Control Logic and State Machines. 7. Data Processing Functions. 8. Combinational Logic and Optimization. 9. Putting the Pieces Together. 10. Evaluating a Synthesis System. 11. Future Prospects for ASIC Synthesis. Appendix A: Reference Materials. Index.
Bitte ändern Sie das Passwort
