Veldhoven / Roermund Robust Sigma Delta Converters

And Their Application in Low-Power Highly-Digitized Flexible Receivers
1. Auflage 2011
ISBN: 978-94-007-0644-6
Verlag: Springer Netherlands
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 296 Seiten

Reihe: Analog Circuits and Signal Processing

Sigma Delta converters are a very popular choice for the A/D converter in multi-standard, mobile and cellular receivers. Key A/D converter specifications are high dynamic range, robustness, scalability, low-power and low EMI. Robust Sigma Delta Converters presents a requirement derivation of a Sigma Delta modulator applied in a receiver for cellular and connectivity, and shows trade-offs between RF and ADC. The book proposes to categorize these requirements in 5 quality indicators which can be used to qualify a system, namely accuracy, robustness, flexibility, efficiency and emission. In the book these quality indicators are used to categorize Sigma Delta converter theory. A few highlights on each of these quality indicators are; Quality indicators: provide a means to quantify system quality.Accuracy: introduction of new Sigma Delta Modulator architectures.Robustness: a significant extension on clock jitter theory based on phase and error amplitude error models. Extension of the theory describing aliasing in Sigma Delta converters for different types of DACs in the feedback loop. Flexibility: introduction of a Sigma Delta converter bandwidth scaling theory leading to very flexible Sigma Delta converters. Efficiency: introduction of new Figure-of-Merits which better reflect performance-power trade-offs. Emission: analysis of Sigma Delta modulators on emission is not part of the bookThe quality indicators also reveal that, to exploit nowadays advanced IC technologies, things should be done as much as possible digital up to a limit where system optimization allows reducing system margins. At the end of the book Sigma Delta converter implementations are shown which are digitized on application-, architecture-, circuit- and layout-level.Robust Sigma Delta Converters is written under the assumption that the reader has some background in receivers and in A/D conversion.

Robert H.M. van Veldhoven was born in Eindhoven, The Netherlands, in 1972. After finishing his pre-education (HAVO) at ''Het Hertog-Jan College'' in Valkenswaard, he started to study ''hands-on'' electronics at the MTS ''Leonardo Da Vinci college'' in Eindhoven. After 2 years at the MTS, he started studying electrical engineering at the polytechnical college ''Fontys Hogescholen'' in Eindhoven. In 1996 he joined the Mixed-Signal Circuits and Systems group at Philips Research after successfully finishing his graduation project on a low-power Sigma Delta modulator for multi-meter applications. After working 3 years at Philips he started to pursue a master degree in Electronics from the Technical University of Eindhoven, which he successfully finished in 2003. After working for 10 years at Philips Research, he joined the Mixed-Signal Circuits and Systems group at NXP Semiconductor Research in Eindhoven in 2006, where he is an expert in the field of high-resolution A/D and D/A converters, and integrated circuits for instrumentation-, sensor-, audio-, and radio-systems. In 2010 he pursued a PhD degree in Electronic Engineering. Van Veldhoven holds various US patents and published various papers at leading conferences and in leading journals, and is reviewer for several professional journals and conferences. In 2004 and 2010, he was invited to give a forum presentation at the ISSCC about sd modulators for wireless and cellular receivers.Arthur H.M. van Roermund (SM'95) was born in Delft, The Netherlands in 1951. He received the M.Sc. degree in electrical engineering in 1975 from the Delft University of Technology and the Ph.D. degree in Applied Sciences from the K.U.Leuven, Belgium, in 1987. From 1975 to 1992 he was with Philips Re­search Laborato­ries in Eindhoven. From 1992 to 1999 he has been a full pro­fessor at the Electrical Engineer­ing Department of Delft Universi­ty of Technol­ogy, where he was chairman of the Elec­tronics Research Group and member of the management team of DIMES. From 1992 to 1999 he has been chairman of a two-years post-graduate school for 'chartered designer'. From 1992 to 1997 he has been consultant for Philips. October 1999 he joined Eindhoven University of Technology as a full professor, chairing the Mixed-signal Microelectronics Group. Since September 2002 he is also director of research of the Department of Electrical Engineering. He is chairman of the board of ProRISC, a nation-wide microelectronics platform; a member of the ICT research platform for the Netherlands (IPN); and a member of the supervisory board of the NRC Photonics research centre. Since 2001, he is one of the three organisers of the yearly workshop on Advanced Analog Circuit Design (AACD). In 2004 he achieved the 'Simon Stevin Meester' award, coupled to a price of 500.000€, for his scientific and technological achievements. In 2007 he was member of an international assessment panel for the Department of Electronics and Information of Politecnico di Milano, and in 2009 for Electronics and Electrical Engineering for the merged Aalto University Finland. He authored/co-authored more than 300 articles and 25 books.  

Autoren/Hrsg.

Veldhoven, Robert H. M. van

Roermund, Arthur H. M. Van

Inhaltsverzeichnis

1;Preface;6
2;Contents;7
3;List of Abbreviations;12
4;Terminology;16
5;List of Symbols;18
6;Nomenclature;21
7;Introduction;22
7.1;Advanced, Multi-standard Cellular and Connectivity Terminals for the Mass Market;23
7.1.1;Complexity: Mobile Phone Trends, Its Impact on the Transceiver and the Quest for Integration;24
7.1.1.1;Implications of Trends on the ADC Specification Generalized in Quality Indicators;27
7.1.2;Transistor Scaling: VLSI and Moore;28
7.1.2.1;Transistor Scaling in the Context of Shannon's Channel-Capacity Theorem;30
7.1.3;Smarter Circuits: Sigma Delta Modulators for Mobile Applications;30
7.2;Book Aims;31
7.3;Book Scope;32
7.4;Outline;32
8;System Quality Indicators;34
8.1;The System Function and Its In- and Outputs;35
8.2;System Quality;36
8.2.1;Accuracy;37
8.2.2;Robustness to Secondary Inputs;37
8.2.3;Flexibility;37
8.2.4;Efficiency;38
8.2.5;Emission of Secondary Outputs;38
8.3;The Digital Revolution;39
8.3.1;The Analog-Digital Interface;40
8.3.2;Digital Systems and the Quality Indicators;41
8.3.2.1;Accuracy;41
8.3.2.2;Robustness;42
8.3.2.3;Flexibility;43
8.3.2.4;Efficiency;43
8.3.2.5;Emission;44
8.4;Conclusions;44
9;Integrated Receiver Architectures for Cellular and Connectivity;48
9.1;Wireless Receiver Architectures for Digital Communication;48
9.2;Receiver Architecture and the Quality Indicators;51
9.3;Conclusions;52
10;Specifications for A/D Converters in Cellular and Connectivity Receivers;53
10.1;IF Choice;54
10.1.1;Image Rejection;54
10.1.2;Zero IF Architecture;55
10.1.3;Near Zero and High IF Architecture;57
10.1.4;IF Assessment;58
10.1.5;DC Offset and 1/f Noise;58
10.1.6;RF Front-End and ADC 1/f-Thermal Noise Corner Frequency;61
10.2;Top-End of the ADC DR;65
10.2.1;Signal Levels, Selectivity, and Maximum ADC Input Signal;66
10.2.2;Crest Factor;68
10.3;Receiver Gain;69
10.3.1;Narrow vs. Broad Band AGC;70
10.4;Bottom-End of the ADC DR;70
10.4.1;Receiver SNR Requirement;70
10.4.2;Receiver Noise Figure and ADC Noise Floor;71
10.5;DR of the ADC;73
10.5.1;DR of a Quadrature ADC;73
10.6;RF Front-End and ADC Linearity Requirements;74
10.6.1;Second and Third Order Harmonic Distortion;74
10.6.2;Second and Third Order Intermodulation and IP2 and IP3;75
10.6.3;Third Order Cross-Modulation;78
10.6.4;Distortion in a Quadrature ADC;79
10.7;Example Receiver Partitioning: Receiver for a GSM Mobile Phone;81
10.7.1;IF Choice and Image Rejection;82
10.7.2;Top-End of the ADC Dynamic Range;83
10.7.3;Receiver Sensitivity Requirement and the Bottom-End of the ADC Dynamic Range;85
10.7.4;Receiver Linearity Requirement and ADC Linearity;86
10.8;ADC Requirements, the System Quality Indicators and Sigma Delta Modulators as the ADC Architecture;87
10.9;Conclusions;90
11;Sigma Delta Modulator Algorithmic Accuracy;91
11.1;Sigma Delta Modulators with 1-bit Quantizer and 1-bit DAC;93
11.2;Sigma Delta Modulators with b-bit Quantizer and b-bit DAC;98
11.3;Sigma Delta Modulators with 1.5-bit Quantizer and DAC;99
11.4;Sigma Delta Modulators with Multiple Quantizers and 1-bit DAC;100
11.5;Sigma Delta Modulators with Additive Error-Feedback Loops;102
11.6;Cascaded Sigma Delta Modulators;107
11.7;Conclusions;108
12;Sigma Delta Modulator Robustness;110
12.1;Portable, Technology Robust Analog IP and Time-to-Market;111
12.1.1;Technology Scaling and Its Impact on Analog Design Parameters;112
12.1.2;A Design Methodology to Increase the Portability of Analog IP;113
12.2;Continuous Time vs. Discrete Time Loop Filter;116
12.3;Feed-Forward vs. Feedback Loop Filter;118
12.4;Gain Accuracy;120
12.4.1;Sigma Delta Modulator with 1-bit Quantizer and 1-bit DAC;120
12.4.2;Sigma Delta Modulator with b-bit Quantizer and b-bit DAC;120
12.4.3;Sigma Delta Modulator with Multiple Quantizers and 1-bit DAC;120
12.4.4;Sigma Delta Modulator with Additive Error Feedback Loops;121
12.4.5;Cascaded Sigma Delta Modulators;123
12.5;Circuit Noise of the Modulator's Input Stage and DAC;124
12.5.1;RC Integrator Input Stage and SI Feedback DAC;124
12.5.2;RC Integrator Input Stage and SR Feedback DAC;125
12.5.3;RC Integrator Input Stage and SC Feedback DAC;125
12.5.4;Impact of Supply Voltage on the Circuit Noise Requirements;126
12.6;Non-linearity;127
12.6.1;Non-linearity in the Input Stage;127
12.6.1.1;Non-linearity of Differential Pairs;128
12.6.1.2;Non-linearity of a Sigma Delta Modulator Input Stage;129
12.6.2;Non-linearity in the Quantizer Decision Levels;130
12.6.3;Inter-Symbol-Interference in the Feedback DAC;131
12.6.4;Non-linearity in the Output Levels of the Feedback DAC;132
12.6.4.1;Non-linearity in the Output Levels of a 1-bit DAC;132
12.6.4.2;Non-linearity in the Output Levels of a b-bit DAC;132
12.6.4.3;Non-linearity in the Output Levels of a 1.5-bit DAC;133
12.7;Aliasing in Sigma Delta Modulators;135
12.7.1;Aliasing in the Quantizer;135
12.7.2;Sigma Delta Modulator with an SI Feedback DAC;136
12.7.2.1;Simulations;138
12.7.3;Sigma Delta Modulator with an SR Feedback DAC;139
12.7.3.1;Mismatch Between Data Switches and RTZ Switch;139
12.7.3.2;Inter Data Switch Mismatch;140
12.7.3.3;Simulations;141
12.7.4;Sigma Delta Modulator with an SC Feedback DAC;141
12.8;Excess Loop Delay;146
12.8.1;Excess Time Delay Compensation;147
12.8.2;Excess Phase Compensation;148
12.8.3;DAC Feedback Pulse Shape and Delay;150
12.9;Clock Jitter in CT Sigma Delta Modulators;151
12.9.1;The TAJE Model;152
12.9.1.1;CT 1-bit Sigma Delta Modulator with SI DAC;153
12.9.1.2;CT 1-bit Sigma Delta Modulator with RTZ SI DAC;153
12.9.1.3;CT 1-bit Sigma Delta Modulator with RTZ SC DAC;155
12.9.1.4;The TAJE Model: SI Versus SC Feedback DAC;156
12.9.1.5;TAJE Model Summary;157
12.9.2;The TPJE Model: Sine Wave Induced Jitter;158
12.9.2.1;Sigma Delta Modulator with SC DAC;159
12.9.2.1.1;Amplitude Modulation;160
12.9.2.1.2;Phase Modulation;160
12.9.2.1.3;Combination of Amplitude and Phase Modulation;161
12.9.2.2;Sigma Delta Modulator with SI DAC;162
12.9.2.2.1;Amplitude Modulation;162
12.9.2.2.2;Phase Modulation;163
12.9.2.2.3;Combination of Amplitude and Phase Modulation;164
12.9.2.3;Application of the Sine Wave Induced Jitter Model;164
12.9.2.4;Verification of the TPJE Model with Sine Wave Induced Clock Jitter;165
12.9.3;The TPJE Model: Substitution of White Noise Jitter in the Sine Wave Induced Jitter Model;170
12.9.3.1;Sigma Delta Modulator with SC DAC;170
12.9.3.2;Sigma Delta Modulator with SI DAC;173
12.9.3.3;Verification of the TPJE Model with White Noise Induced Clock Jitter;175
12.9.4;The TPJE Model: SI Versus SC Feedback DAC;180
12.9.5;The TPJE Model: An Application Driven Choice Between SI Versus SC Feedback DAC;181
12.9.5.1;Modulators with a Top-End DR Determined by In-band Signals;181
12.9.5.2;Modulators with a Top-End DR Determined by Out-of-Band Signals;183
12.10;Conclusions;188
13;Sigma Delta Modulator Flexibility;194
13.1;Receiver Dictated Flexibility Requirements;194
13.2;Sigma Delta Modulator Clock Flexibility;196
13.2.1;Receiver Architecture with LO-Dependent ADC Clock;197
13.2.2;Receiver Architecture with a Flexible and Independent Clock for the ADC;198
13.2.3;Receiver Architecture with Fixed, Independent ADC Clock;199
13.2.4;Choice of Clock Strategy;201
13.3;Input Stage and DAC Flexibility;202
13.4;Loop-Filter Flexibility;202
13.5;Quantizer Flexibility;204
13.6;Conclusions;205
14;Sigma Delta Modulator Efficiency;207
14.1;Power Efficiency FOM: FOMDR;209
14.1.1;Benchmarking with FOMDR;211
14.2;Power Efficiency FOM: FOMeq,th;212
14.2.1;Benchmarking with FOMeq,th;215
14.3;Distortion FOM: FOMHD3D;218
14.3.1;Benchmarking with FOMHD3D;220
14.4;Area FOM: FOMarea;223
14.4.1;Benchmarking with FOMarea;227
14.5;Conclusions;229
15;Sigma Delta Modulator Implementations and the Quality Indicators;230
15.1;Digitization at System/Application Level: Sigma Delta Modulators for Highly Digitized Receivers;231
15.1.1;A 1.5-bit Sigma Delta Modulator for UMTS;232
15.1.1.1;System Architecture;232
15.1.1.2;Modulator Architecture;232
15.1.1.3;Circuit Design;234
15.1.1.4;Experimental Results;236
15.1.1.5;Conclusions;238
15.1.2;A Triple-Mode Sigma Delta Modulator for GSM-EDGE, CDMA2000 and UMTS;239
15.1.2.1;System Architecture;240
15.1.2.2;Sigma Delta Modulator Architecture;240
15.1.2.3;Circuit Design;242
15.1.2.4;Experimental Results;245
15.1.2.5;Conclusions;248
15.1.3;An Extremely Scalable Sigma Delta Modulator for Cellular and Wireless Applications;249
15.1.3.1;System Architecture;249
15.1.3.2;Sigma Delta Modulator Architecture;249
15.1.3.3;Experimental Results;252
15.1.3.4;Conclusions;255
15.1.4;Multi-mode Modulator Clock Strategy;255
15.2;Digitization at Analog IP Architecture Level: A Hybrid, Inverter-Based Sigma Delta Modulator;257
15.2.1;Sigma Delta Modulator Architecture;258
15.2.2;Circuit Design;259
15.2.3;Experimental Results;262
15.2.4;Conclusions;265
15.3;Digitization at Circuit and Layout Level: Technology Portable Sigma Delta Modulators;266
15.3.1;Sigma Delta Modulator Architecure;267
15.3.2;Circuit Design and Layout;268
15.3.2.1;Experimental Results;271
15.3.3;Conclusions;273
15.4;Implementations Judged on the FOMs and Quality Indicators;274
15.5;Conclusions;277
16;Conclusions;279
17;Harmonic and Intermodulation Distortion in an I&Q System;281
17.1;Double Sided Spectrum of Second and Third Order Distortion of a Complex Signal;281
17.2;Double Sided Spectrum of Second and Third Order Distortion in a Complex System;282
18;Distortion of a Differential Input Transistor Pair Biased in Weak Inversion;284
19;Fourier Series Expansion and Return-to-Zero;285
20;Clock Jitter in an I&Q System According to the TPJE Clock Jitter Model;286
21;References;288
22;Index;301