Latchup in CMOS Technology

The Problem and Its Cure
1986
ISBN: 978-0-89838-215-0
Verlag: Springer US

Buch, Englisch, 244 Seiten, Format (B × H): 160 mm x 241 mm, Gewicht: 1220 g

Reihe: The Springer International Series in Engineering and Computer Science

Why a book on Iatchup? Latchup has been, and continues to be, a potentially serious CMOS reliability concern. This concern is becoming more widespread with the ascendency of CMOS as the dominant VLSI technology, particularly as parasitic bipolar characteristics continue to improve at ever smaller dimensions on silicon wafers with ever lower defect densities. Although many successful parts have been marketed, latchup solutions have often been ad hoc. Although latchup avoidance techniques have been previously itemized, there has been little quantitative evaluation of prior latchup fixes. What is needed is a more general, more systematic treatment of the latchup problem. Because of the wide variety of CMOS technologies and the long term interest in latchup, some overall guiding principles are needed. Appreciating the variety of possible triggering mechanisms is key to a real understanding of latchup. This work reviews the origin of each and its effect on the parasitic structure. Each triggering mechanism is classified according to a new taxonomy.

Zielgruppe

Research

Autoren/Hrsg.

Troutman, R. R.

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Elektronische Baugruppen, Elektronische Materialien

Inhaltsverzeichnis

1. Introduction.- 2. Latchup Overview.- 3. Problem Description.- 4. Latchup Models and Analyses.- 5. Latchup Characterization.- 6. Avoiding Latchup.- 7. Summary.- Appendices.- A. Stability Considerations for PNPN Current-Voltage Measurements.- B. Possible Latchup Characterization Problems.- References.- Glossary: Symbol Definitions.- About the Author.