Taraate PLD Based Design with VHDL

RTL Design, Synthesis and Implementation
1. Auflage 2017
ISBN: 978-981-10-3296-7
Verlag: Springer Singapore
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 429 Seiten, eBook

This book covers basic fundamentals of logic design and advanced RTL design concepts using VHDL. The book is organized to describe both simple and complex RTL design scenarios using VHDL. It gives practical information on the issues in ASIC prototyping using FPGAs, design challenges and how to overcome practical issues and concerns. It describes how to write an efficient RTL code using VHDL and how to improve the design performance. The design guidelines by using VHDL are also explained with the practical examples in this book. The book also covers the ALTERA and XILINX FPGA architecture and the design flow for the PLDs. The contents of this book will be useful to students, researchers, and professionals working in hardware design and optimization. The book can also be used as a text for graduate and professional development courses.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Taraate, Vaibbhav

Inhaltsverzeichnis

Introduction to HDL.- Basic Logic Circuits and VHDL Description.- VHDL Language and Constructs.- Combinational Logic Design and Verification using VHDL Constructs.- Sequential Logic Design using VHDL Constructs.- Introduction to PLD.- VHDL Language Constructs.- PLD based Design Guidelines.- Complex Design and Verification using VHDL and PLDs.- Finite State Machines and PLD based Design.- PLD Design Implementation Flow and Case Study.- Appendix I: VHDL 87 and VHDL 93 Description Styles.- Appendix II: VHDL Design Library and Constructs.- Appendix III: Synthesis Results for Pipelined Processor.

Über Autor(innen)

Vaibbhav Taraate is Entrepreneur and Mentor at "Semiconductor Training @ Rs.1". He holds a BE (Electronics) degree from Shivaji University, Kolhapur in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his MTech (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 15 Years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.