Tan / Gutmann / Reif Wafer Level 3-D ICs Process Technology

1. Auflage 2009
ISBN: 978-0-387-76534-1
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 410 Seiten

Reihe: Integrated Circuits and Systems

This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

Autoren/Hrsg.

Tan, Chuan Seng

Gutmann, Ronald J.

Reif, L. Rafael

Inhaltsverzeichnis

1;Foreword;6
2;Preface;8
3;Contents;10
4;Contributors;12
5;1 Overview of Wafer-Level 3D ICs;16
5.1;1.1 Background and Introduction;16
5.2;1.2 Motivations -- A More than Moore Approach;18
5.2.1;1.2.1 Interconnect Bottleneck;18
5.2.2;1.2.2 Chip Form Factor;19
5.2.3;1.2.3 Heterogeneous Integration;19
5.2.4;1.2.4 Stacked CMOS;19
5.3;1.3 Classification of 3D ICs;20
5.3.1;1.3.1 Monolithic Approaches;21
5.3.2;1.3.2 Assembly Approaches;21
5.3.3;1.3.3 Wafer-Level 3D Design Opportunities;23
5.4;1.4 Organization of the Book;24
6;2 Monolithic 3D Integrated Circuits;27
6.1;2.1 Introduction;27
6.2;2.2 Three-Dimensional Circuits Using Large-Grain Upper Layers;28
6.2.1;2.2.1 Upper-Layer Recrystallization Techniques;28
6.2.1.1;2.2.1.1 Laser Recrystallization;28
6.2.1.2;2.2.1.2 Epitaxial Overgrowth and Solid-Phase Crystallization;29
6.2.2;2.2.2 Three-Dimensional Logic Process Architectures;30
6.2.2.1;2.2.2.1 Common-Gate Processes;30
6.2.2.2;2.2.2.2 Independent Gate Processes;31
6.3;2.3 Three-Dimensional Circuits Using Small-Grained Polysilicon Layers;33
6.3.1;2.3.1 SRAM;33
6.3.2;2.3.2 Nonvolatile Memory: Cross-Point Memories;34
6.3.2.1;2.3.2.1 Cross-Point Memory Architectures;34
6.3.2.2;2.3.2.2 Diode/Antifuse Cross-Point Memory: Technology;35
6.3.2.3;2.3.2.3 Diode/Antifuse Cross-Point Memory: Die Size Considerations;36
6.3.3;2.3.3 Nonvolatile Memory: TFT-SONOS;38
6.4;2.4 Non-Silicon Monolithic 3D Integrated Circuits;40
6.5;2.5 Summary;41
7;3 Stacked CMOS Technologies;44
7.1;3.1 Stacked Complementary Metal-Oxide Semiconductor Topology;44
7.2;3.2 Stacked CMOS Processes and Device Design;46
7.2.1;3.2.1 Layer-by-Layer Process;46
7.2.2;3.2.2 Simultaneous Multilayer Processing;47
7.2.2.1;3.2.2.1 Gate Definition of Lower Layers;47
7.2.2.2;3.2.2.2 Doping the Bottom Layer;48
7.2.2.3;3.2.2.3 Making Contact Between Two Active Layers;49
7.2.3;3.2.3 Layout Issues;50
7.3;3.3 Stacked CMOS on the Thin Film and the Substrate of a SOI Wafer;51
7.4;3.4 Stacked FinCMOS Technology;54
7.5;3.5 Summary;60
8;4 Wafer-Bonding Technologies and Strategies for 3D ICs;61
8.1;4.1 Introduction;61
8.2;4.2 Wafer-Bonding Equipment Overview;61
8.3;4.3 Surface Preparation Treatments;63
8.3.1;4.3.1 Surface Preparation Treatments -- Wet Chemistry;63
8.3.2;4.3.2 Surface Preparation Treatments -- Plasma Activation;65
8.3.3;4.3.3 Surface Preparation Treatments -- Combined Plasma and Wet Chemistry;66
8.3.4;4.3.4 Surface Preparation Treatments -- Vapor Cleaning;67
8.4;4.4 Bond Aligner -- Equipment Working Principle;70
8.5;4.5 Alignment Strategies;71
8.6;4.6 Wafer Transfer Fixtures;78
8.7;4.7 Wafer-Bonding Technology;81
8.7.1;4.7.1 Bond Chamber Design and Components;81
8.8;4.8 Wafer-Bonding Techniques for 3D;84
8.8.1;4.8.1 Silicon Direct Bonding;84
8.8.2;4.8.2 BCB Bonding;85
8.8.3;4.8.3 Coppert-to-Copper Diffusion Bonding;87
8.8.4;4.8.4 Eutectic Bonding;90
8.9;4.9 Bond Quality Testing;92
8.10;4.10 Summary;93
9;5 Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies;96
9.1;5.1 Introduction;96
9.2;5.2 Through-Silicon Vias Compared with Wirebonds;96
9.3;5.3 Through-Silicon Via Hole Formation;97
9.3.1;5.3.1 TSVs for Die-to-Wafer Stacking: Laser Drilling;98
9.3.2;5.3.2 TSVs for Die-to-Wafer Stacking: Etching;98
9.3.3;5.3.3 TSVs for Wafer-to-Wafer Stacking;100
9.4;5.4 Dielectric Liner for TSVs;101
9.5;5.5 Tungsten Via Fill and Polish;103
9.5.1;5.5.1 Contact/Seed/CVD Tungsten Depositions;103
9.6;5.6 Copper Via Fill;103
9.6.1;5.6.1 Barrier and Seed Layers for Copper Plating;103
9.6.2;5.6.2 Electroplating Copper;105
9.6.3;5.6.3 Chemical--Mechanical Polish (CMP) of Copper;106
9.7;5.7 Wafer Thinning;106
9.7.1;5.7.1 Backgrind;106
9.7.2;5.7.2 Wet Etching Silicon to Thin the Wafer and Relieve Stress from Grinding;109
9.7.3;5.7.3 Fracturing Wafers at a Hydrogen Implant-Damaged Plane;109
9.8;5.8 Singulation;110
9.9;5.9 Handle Wafer Technologies;112
9.9.1;5.9.1 Substrate;113
9.9.2;5.9.2 Bonding Layer;114
9.9.2.1;5.9.2.1 Bond Strength;114
9.9.2.2;5.9.2.2 Maximum-Use Temperature;114
9.9.2.3;5.9.2.3 Chemical Stability;114
9.9.2.4;5.9.2.4 Vacuum Compatibility;115
9.9.2.5;5.9.2.5 Final Thickness and Planarity;115
9.9.2.6;5.9.2.6 Releasibility;115
9.9.3;5.9.3 Optional Release Layer;116
9.10;5.10 Wafer-Bonding Methods;116
9.10.1;5.10.1 Thermoplastic Materials;116
9.10.2;5.10.2 UV-Curable Materials;118
9.10.3;5.10.3 Laminates;119
9.10.4;5.10.4 Metal Based;120
9.11;5.11 Handle Wafer Use;120
9.12;5.12 Wafer Debonding Methods;122
9.12.1;5.12.1 Chemical Methods;122
9.12.2;5.12.2 Thermal Methods;122
9.12.3;5.12.3 Laser Treatment;124
9.13;5.13 Post-release Treatments;124
9.14;5.14 Summary, Conclusions, and Future Projections;124
10;6 Cu Wafer Bonding for 3D IC Applications;128
10.1;6.1 Introduction;128
10.2;6.2 Classification of Cu-Bonding Techniques;128
10.2.1;6.2.1 Surface-Activated Cu Bonding;128
10.2.2;6.2.2 Thermal Compression Cu Bonding;129
10.3;6.3 Fundamental Properties of Cu Bonding;129
10.3.1;6.3.1 Morphology of Cu-Bonded Layer;130
10.3.2;6.3.2 Oxide Examination of Cu-Bonded Layer;130
10.3.3;6.3.3 Microstructure Evolution During Cu Bonding;131
10.3.4;6.3.4 Orientation Evolution During Cu Bonding;132
10.4;6.4 Cu-Bonding Development;133
10.4.1;6.4.1 Structural Design;133
10.4.2;6.4.2 Copper Pad Fabrication;134
10.4.3;6.4.3 Bond Parameters;134
10.5;6.5 Cu Bond Quality Characterization and Alignment Accuracy;135
10.6;6.6 Reliable Cu Bonding and Multilayer Stacking;137
10.7;6.7 Applications of Cu Wafer Bonding;139
10.8;6.8 Summary;140
11;7 Cu/Sn Solid-Liquid Interdiffusion Bonding;142
11.1;7.1 The Principle of Solid--Liquid Interdiffusion;143
11.1.1;7.1.1 Liquefaction and Liquid Phase Properties;144
11.1.1.1;7.1.1.1 Characteristics of Soldering with Thin Solder Layers;144
11.1.1.2;7.1.1.2 Hydrostatics of the Solder Pad;146
11.1.2;7.1.2 Metallurgy and Intermetallic Growth;147
11.1.2.1;7.1.2.1 Phase Front Propagation in Cu/Sn Diffusion Couples;148
11.1.2.2;7.1.2.2 Calculation of the Metal Pad Thickness;150
11.1.3;7.1.3 Process Conditions and Characteristics;151
11.1.3.1;7.1.3.1 Surface Metal Oxides;151
11.1.3.2;7.1.3.2 Parasitic Consumption of Reactive Solder;151
11.1.3.3;7.1.3.3 Wetting versus Intermetallic Growth;153
11.1.3.4;7.1.3.4 Electromigration;153
11.2;7.2 Chip-Stacking: The SOLID-F2F Process;154
11.2.1;7.2.1 Process Flow;155
11.2.2;7.2.2 Behavior of Underfill in Small Gaps;156
11.2.3;7.2.3 Self-Alignment;158
11.2.4;7.2.4 Reliability Results;158
11.2.4.1;7.2.4.1 Thermal Cycling;159
11.2.4.2;7.2.4.2 High-Temperature Storage;159
11.2.4.3;7.2.4.3 Corrosion;160
11.2.4.4;7.2.4.4 Electromigration;162
11.3;7.3 Three-Dimensional Integration: SLID for Multichip Stacking;163
11.3.1;7.3.1 Scheme with SLID and Backside Vias;164
11.3.1.1;7.3.1.1 Basic Considerations;164
11.3.1.2;7.3.1.2 Preprocessing;165
11.3.1.3;7.3.1.3 Processing;165
11.3.1.4;7.3.1.4 Stack Building;168
11.3.1.5;7.3.1.5 Results;169
11.3.2;7.3.2 Scheme with ICV-SLID Technology;170
11.3.2.1;7.3.2.1 Processes;170
11.3.2.2;7.3.2.2 Results;172
11.3.3;7.3.3 Scheme with Copper Bump Bonding;172
11.3.3.1;7.3.3.1 Process Scheme;173
11.3.3.2;7.3.3.2 CBB Process;173
11.4;7.4 Brief Discussion on W2W Versus C2W Schemes;175
11.5;7.5 Conclusion;176
12;8 An SOI-Based 3D Circuit Integration Technology;181
12.1;8.1 Introduction;181
12.2;8.2 Lincoln Laboratory's Wafer-Scale 3D Circuit Integration Technology;182
12.2.1;8.2.1 Three-Dimensional Fabrication Process;182
12.2.2;8.2.2 Three-Dimensional Enabling Technologies;184
12.2.3;8.2.3 Three-dimensional Technology Scaling;189
12.3;8.3 Transferred FDSOI Transistor and Device Properties;191
12.4;8.4 Multiproject Circuit Design and Layout in Lincoln Laboratory's 3D Technology;193
12.4.1;8.4.1 Three-Dimensional Design and Layout Practice;194
12.4.2;8.4.2 Computer-Aided Design Tool Refinements;194
12.4.3;8.4.3 Three-Dimensional Design Optimization;195
12.4.4;8.4.4 Wafer--Wafer Alignment Aids;196
12.4.5;8.4.5 Three-Dimensional Design and Submission Procedures;198
12.4.6;8.4.6 Three-Dimensinal Circuit Design Examples;198
12.5;8.5 Three-Dimensional Circuit and Device Results;201
12.5.1;8.5.1 Three-Dimensional-LADAR Chip;201
12.5.2;8.5.2 1024 1024 3D Visible Imager;203
12.5.3;8.5.3 Heterogeneous Integration;204
12.6;8.6 Summary;204
13;9 3D Fabrication Options for High-Performance CMOS Technology;207
13.1;9.1 3-D Technology;207
13.1.1;9.1.1 Introduction;207
13.1.2;9.1.2 Three-Dimensional Technology Landscape;208
13.1.3;9.1.3 Wafer-Level 3D Integration;209
13.1.4;9.1.4 IBM 3D Integration Approaches;211
13.1.4.1;9.1.4.1 Copper Bonding with TSVs for Processor/Memory Stacking;211
13.1.4.2;9.1.4.2 SOI-Based 3D Integration for Ultrahigh-Density and Device-Level Stacking;216
13.2;9.2 Future Development Activities for 3D Integration;222
13.2.1;9.2.1 Thermal Dissipation in Bonded Structures;222
13.2.2;9.2.2 Noise in 3D Integrated Structures;223
13.2.3;9.2.3 Bandwidth Utilization and Smart Power-Efficient Designs (Lower-Power Voltage Operations, Energy Efficiency);223
13.2.3.1;9.2.3.1 Bandwidth Advantages of 3D;223
13.2.4;9.2.4 Power-Efficient 3D Possibilities;224
13.3;9.3 Summary;225
14;10 3D Integration Based upon Dielectric Adhesive Bonding;228
14.1;10.1 Introduction;228
14.2;10.2 Adhesive Bonding Mechanisms and Dielectric Adhesives;229
14.2.1;10.2.1 Desired Properties of Polymer Adhesive Materials for Wafer Bonding;230
14.2.2;10.2.2 Adhesive Wafer-Bonding Technology;231
14.3;10.3 Wafer-Level 3D Integration Platforms Based upon Adhesive Bonding;234
14.3.1;10.3.1 Via-Last 3D Platform Using Blanket Adhesive Wafer Bonding and Cu Damascene Interstrata Interconnects;236
14.3.2;10.3.2 Via-First 3D Platform with Wafer-Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers;236
14.4;10.4 Impacts of Soft-Baked BCB and Partially Cured BCB;238
14.4.1;10.4.1 Thickness Uniformity of BCB Layers;239
14.4.2;10.4.2 BCB Bond Strength and Impact on Bonding Void and Defects;240
14.4.3;10.4.3 Impact on Wafer-to-Wafer Alignment Accuracy;241
14.5;10.5 Integrity Characterizations of Blanket Adhesive Wafer Bonding;242
14.5.1;10.5.1 Optical Inspection Using Glass Wafer;242
14.5.2;10.5.2 Bonding Strength Characterization Using Four-Point Bending;243
14.5.3;10.5.3 Thermal Cycling Test;245
14.5.4;10.5.4 Packaging Reliability Tests;245
14.5.5;10.5.5 Wafer Thinning;246
14.5.6;10.5.6 Electrical Characterization of Adhesive Wafer-Bonding Integrity;247
14.6;10.6 Integrity Characterizations of Patterned/Processed Adhesive Wafer Bonding;249
14.6.1;10.6.1 Partially Cured BCB for Copper Damascene Patterning;250
14.6.2;10.6.2 Bond Strength and Voids/Defects;251
14.6.3;10.6.3 Surface Topography of Damascene-Patterned Cu/BCB Layer;251
14.7;10.7 Feasibility Demonstrations of Wafer-Level 3D Integration;252
14.7.1;10.7.1 Via-Last 3D Platform Feasibility Demonstration;252
14.7.2;10.7.2 Via-First 3D Platform Feasibility Demonstration;254
14.8;10.8 Thermomechanical Modeling;257
14.9;10.9 General Discussions on 3D Platforms and Applications;259
14.10;10.10 Conclusions;261
15;11 Direct Hybrid Bonding;266
15.1;11.1 Introduction;266
15.2;11.2 The Direct Hybrid Bonding Process;268
15.2.1;11.2.1 TSV Die Preparation;268
15.2.2;11.2.2 Preparation of the Landing Surface: Dielectric Application and Patterning;270
15.3;11.3 Choice of Metal Bond Type and Dielectric;273
15.4;11.4 Collective Hybrid Bonding;274
15.4.1;11.4.1 Requirements for Pick-and-Place;275
15.4.2;11.4.2 Compliant Bonding;275
15.5;11.5 Summary;276
16;12 3D Memory;277
16.1;12.1 A Brief History of Memory;277
16.2;12.2 3D Memory By Many Means;277
16.2.1;12.2.1 3D Packaging;277
16.2.2;12.2.2 3D ICs;279
16.2.2.1;12.2.2.1 Separate Fabrication or Sequential Fabrication?;281
16.2.2.2;12.2.2.2 Wafer Scale or Device Scale?;282
16.3;12.3 DRAM;282
16.3.1;12.3.1 DRAM Manufacturing;282
16.3.2;12.3.2 Simplified DRAM Overview;283
16.3.3;12.3.3 DRAM Construction Issues;283
16.3.4;12.3.4 Array Efficiency;286
16.3.5;12.3.5 The Memory Wall;286
16.3.6;12.3.6 Repair and Redundancy, Test, and Reliability;287
16.3.7;12.3.7 3D Benefits in DRAM;289
16.4;12.4 Building 3D DRAM;289
16.4.1;12.4.1 Latency;290
16.4.2;12.4.2 Power;291
16.4.3;12.4.3 Reliability;291
16.4.4;12.4.4 Cost;292
16.4.4.1;12.4.4.1 Memory Wafer Processing;292
16.4.4.2;12.4.4.2 Array Efficiency;292
16.4.4.3;12.4.4.3 Testing;293
16.4.4.4;12.4.4.4 Improved Yield;293
16.4.5;12.4.5 Other Benefits of 3D Memory;294
16.5;12.5 Tezzaron 3D Process Flow;294
16.6;12.6 Embedded Memory versus Stacked Memory;297
16.7;12.7 3D Futures;298
17;13 Circuit Architectures for 3D Integration;300
17.1;13.1 Introduction;300
17.2;13.2 Three-Dimensional SOC;301
17.2.1;13.2.1 Parasitic Coupling;302
17.3;13.3 Digital Systems;304
17.3.1;13.3.1 Imager Systems;304
17.3.2;13.3.2 Interconnect-Dominated Systems;305
17.4;13.4 Nanoscale/Microscale Integration;308
17.5;13.5 Comparison Between 3D Integration and Planar Packaging;311
18;14 Thermal Challenges of 3D ICs;313
18.1;14.1 Introduction;313
18.2;14.2 Thermal Effects in 3D ICs in the Nanometer Regime;315
18.2.1;14.2.1 Impact of Heat on Device and Interconnect Reliability;315
18.2.2;14.2.2 Analytical Average Die Temperature Model;315
18.2.3;14.2.3 Origin and Significance of Electrothermal Couplings;317
18.3;14.3 Self-Consistent Temperature Estimation for 3D ICs;319
18.3.1;14.3.1 Typical Chip Package Structure and Heat Transfer Mechanisms;320
18.3.2;14.3.2 Full-Chip Package Thermal Model;321
18.3.3;14.3.3 Numerical Approach and Methodology Overview;323
18.3.4;14.3.4 Setup and Implementation: An Example of a 2D IC Thermal Profile Estimation;326
18.3.5;14.3.5 3D IC Thermal Profile Estimation: Analysis and Implications;329
18.4;14.4 Implications and Opportunities for 3D IC Thermal Management;333
18.5;14.5 Summary;335
19;15 Status and Outlook;339
19.1;15.1 Introduction;339
19.2;15.2 Technology and Applications;339
19.2.1;15.2.1 System Integration;339
19.2.2;15.2.2 Vertical Interconnect;341
19.2.2.1;15.2.2.1 Vertical Interconnect Density and Applications;342
19.2.2.2;15.2.2.2 Interstratum Connections;343
19.2.2.3;15.2.2.3 Through-Stratum Vias;343
19.2.3;15.2.3 Bonded Vertical Integration Technologies;345
19.2.3.1;15.2.3.1 Alignment and Bonding;345
19.2.3.2;15.2.3.2 Stratum Thinning;347
19.2.4;15.2.4 Design;347
19.3;15.3 Packaging of 3D Devices;349
19.3.1;15.3.1 Signal, Power, and Ground Congestion;349
19.3.2;15.3.2 Thermal Congestion and Heat Dissipation;350
19.3.3;15.3.3 Reliability of Packaged 3D Devices;350
19.4;15.4 Market and Economics of 3D;351
19.4.1;15.4.1 Technology Maturity;351
19.4.2;15.4.2 Cost;351
19.5;15.5 Market Projections;354
20;Index;359