Szefer / Tessier Security of FPGA-Accelerated Cloud Computing Environments

1. Auflage 2023
ISBN: 978-3-031-45395-3
Verlag: Springer International Publishing
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 328 Seiten, eBook

This book addresses security of FPGA-accelerated cloud computing environments. It presents a comprehensive review of the state-of-the-art in security threats as well as defenses. The book further presents design principles to help in the evaluation and designs of cloud-based FPGA deployments which are secure from information leaks and potential attacks.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Szefer, Jakub

Tessier, Russell

Inhaltsverzeichnis

Introduction to, and history of, Cloud FPGAs.- FPGA device level security issues and countermeasures.- FPGA interfacing security issues (buses attacks, memory interfaces, etc.- IP protection for FPGAs in the cloud.- Software system security for cloud FPGAs (hypervisor leaks, shared memory use).- Cross-node/network security – (e.g., voltage attack across nodes, network flooding by FPGAs).- Likely future attacks.- Summary and conclusion.

Über Autor(innen)

Jakub Szefer’s research focuses on computer architecture and hardware security. His research encompasses secure processor architectures, cloud security, FPGA attacks and defenses, and hardware FPGA implementation of cryptographic algorithms. His research is supported through the National Science Foundation and industry grants and donations. He is currently an Associate Professor of Electrical Engineering at Yale University, where he leads the Computer Architecture and Security Laboratory (CASLAB). Prior to joining Yale, he received Ph.D. and M.A. degrees in Electrical Engineering from Princeton University, and B.S. degree with highest honors in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign. He received the NSF CAREER award in 2017. Jakub is the author of the first book focusing on processor architecture security: “Principles of Secure Processor Architecture Design”, published in 2018. He was promoted to the IEEE Senior Member rank in 2019.

Russell Tessier’s research interests are in field-programmable gate arrays (FPGAs), reconfigurable computing, and embedded systems. His research program includes the development of new applications of FPGAs for network virtualization, radar processing, and communication coding. Most recently, he has examined the security of FPGA use in computing environments. Dr. Tessier’s research is funded by the National Science Foundation, state government, and industry grants and donations. He is Professor of Electrical and Computer Engineering at the University of Massachusetts Amherst, where he serves as the head of the Reconfigurable Computing Group. He received S.M. and Ph.D. degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology, and a B.S. degree in Computer Systems Engineering from Rensselaer Polytechnic Institute. He was a co-founder of Virtual Machine Works, a company that manufactured FPGA-based logic emulators. The company is now owned by Siemens which markets the product under the Veloce brand.