Swingler Reliability Characterisation of Electrical and Electronic Systems

1. Auflage 2014
ISBN: 978-1-78242-225-9
Verlag: Elsevier Science & Techn.
Format: EPUB
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, Band 74, 274 Seiten

Reihe: Woodhead Publishing Series in Electronic and Optical Materials

This book takes a holistic approach to reliability engineering for electrical and electronic systems by looking at the failure mechanisms, testing methods, failure analysis, characterisation techniques and prediction models that can be used to increase reliability for a range of devices.

Autoren/Hrsg.

Swingler, Jonathan

Inhaltsverzeichnis

1;Front Cover;1
2;Reliability Characterisation of Electrical and Electronic Systems;4
3;Copyright;5
4;Contents;6
5;List of contributors;10
6;Woodhead Publishing Series in Electronic and Optical Materials;12
7;Foreword;16
8;Chapter 1: Introduction;18
8.1;1.1. Introduction;18
8.2;1.2. The focus of the book;18
8.2.1;1.2.1. Reliability characterisation;19
8.2.2;1.2.2. Electrical and electronic systems;20
8.2.3;1.2.3. The readers and the contributing authors;20
8.3;1.3. Reliability science and engineering fundamentals (Chapters 2-4Chapter 2Chapter 3Chapter 4);20
8.3.1;1.3.1. Reliability and stupidity;21
8.3.2;1.3.2. Physics-of-failure thinking;22
8.3.3;1.3.3. Acquiring observational evidence;23
8.4;1.4. Reliability methods in component and system development (Chapters 5-9Chapter 5Chapter 6Chapter 7Chapter 8Chapter 9);23
8.4.1;1.4.1. Components and devices;24
8.4.2;1.4.2. Micro- and nanointegrated circuits;24
8.4.3;1.4.3. More complex systems;25
8.5;1.5. Reliability modelling and testing in specific applications (Chapters 10 and 11Chapter 10Chapter 11);25
8.5.1;1.5.1. Application examples;25
8.5.2;1.5.2. Verification techniques;26
8.5.3;1.5.3. Block modelling with ALT techniques;26
8.6;1.6. Conclusion;26
8.7;References;27
9;Chapter 2: Reliability and stupidity;28
9.1;2.1. Introduction;28
9.2;2.2. Common mistakes in reliability engineering;29
9.2.1;2.2.1. Inadequate integration of reliability engineering with product development;30
9.2.2;2.2.2. Focus on ``probability´´ in conventional definition of reliability engineering;32
9.2.3;2.2.3. Quantification of reliability;33
9.2.4;2.2.4. Ignoring cause and effect relationship in reliability engineering;34
9.2.5;2.2.5. Incorrect understanding of the meaning of MTBF;35
9.2.6;2.2.6. Inadequate failure testing during product development;36
9.2.7;2.2.7. Reliability engineering activities performed at incorrect time during development;36
9.2.8;2.2.8. Reliability engineering activities performed by incorrect personnel;37
9.2.9;2.2.9. Non-value adding reliability engineering activities;38
9.2.10;2.2.10. Incorrect viewpoint on cost of reliability;39
9.3;2.3. Conclusion;41
9.4;References;41
10;Chapter 3: Physics-of-failure (PoF) methodology for electronic reliability;44
10.1;3.1. Introduction;44
10.2;3.2. Reliability;44
10.3;3.3. PoF models;46
10.4;3.4. PoF reliability assessment;49
10.5;3.5. Applications of PoF to ensure reliability;51
10.6;3.6. Summary and areas of future interest;54
10.7;References;55
11;Chapter 4: Modern instruments for characterizing degradation in electrical and electronic equipment;60
11.1;4.1. Introduction;60
11.1.1;4.1.1. Modern instruments;60
11.2;4.2. Destructive techniques;60
11.2.1;4.2.1. Cross sections;60
11.2.2;4.2.2. Jet etching and depotting components;62
11.2.3;4.2.3. Chemical analysis;63
11.2.3.1;4.2.3.1. Ion chromatography;63
11.2.3.2;4.2.3.2. Infrared spectroscopy;63
11.2.3.3;4.2.3.3. Raman spectroscopy;65
11.2.3.4;4.2.3.4. Mass spectrometric techniques;66
11.2.3.5;4.2.3.5. SEM imaging with energy-dispersive X-ray and wavelength-dispersive X-ray analyses;67
11.2.3.6;4.2.3.6. Focused ion beam sample preparation;68
11.2.3.7;4.2.3.7. Transmission electron microscopy (TEM);68
11.3;4.3. Nondestructive techniques;69
11.3.1;4.3.1. Visual inspection;69
11.3.2;4.3.2. Optical microscopy;69
11.3.2.1;4.3.2.1. Stereomicroscopes;69
11.3.2.2;4.3.2.2. Metallurgical microscopes;70
11.3.2.3;4.3.2.3. Transmission microscopes;70
11.3.2.4;4.3.2.4. Combination systems;70
11.3.3;4.3.3. X-ray imaging techniques;71
11.3.4;4.3.4. Infrared thermography;72
11.3.5;4.3.5. X-ray fluorescence analysis;72
11.3.6;4.3.6. Acoustic microscopy;73
11.4;4.4. In situ measurement techniques;74
11.4.1;4.4.1. Electrical measurements;74
11.4.1.1;4.4.1.1. Electrical conductivity/resistivity measurement;75
11.4.1.2;4.4.1.2. Passive component measurement;76
11.4.2;4.4.2. Measurement of physical characteristics;76
11.4.2.1;4.4.2.1. Profilometer surface roughness;76
11.4.2.2;4.4.2.2. Atomic force microscopy;77
11.5;4.5. Conclusions;78
11.5.1;4.5.1. Future trends;78
11.5.2;4.5.2. Sources of further information;78
11.5.3;References;79
12;Chapter 5: Reliability building of discrete electronic components;80
12.1;5.1. Introduction;80
12.2;5.2. Reliability building;80
12.2.1;5.2.1. Design for reliability;81
12.2.2;5.2.2. Process reliability;82
12.2.3;5.2.3. Screening and burn-in;82
12.3;5.3. Failure risks and possible corrective actions;84
12.3.1;5.3.1. Discrete electronic components;84
12.3.2;5.3.2. Capacitors;84
12.3.2.1;5.3.2.1. Aluminum electrolytic capacitors;84
12.3.2.2;5.3.2.2. Tantalum capacitors;86
12.3.3;5.3.3. Diodes;86
12.3.3.1;5.3.3.1. Silicon diodes;87
12.3.3.2;5.3.3.2. Nonsilicon diodes;89
12.3.4;5.3.4. Transistors;92
12.3.4.1;5.3.4.1. Silicon transistors;92
12.3.4.2;5.3.4.2. Nonsilicon transistors;94
12.4;5.4. Effect of electrostatic discharge on discrete electronic components;95
12.4.1;5.4.1. Electrostatic discharge (ESD);95
12.4.2;5.4.2. ESD-induced failures;95
12.4.3;5.4.3. ESD robust systems;95
12.5;5.5. Conclusions;96
12.6;References;96
13;Chapter 6: Reliability of optoelectronics;100
13.1;6.1. Introduction;100
13.2;6.2. Overview of optoelectronics reliability;101
13.3;6.3. Approaches and recent developments;102
13.4;6.4. Case study: reliability of buried heterostructure (BH) InP semiconductor lasers;107
13.4.1;6.4.1. Effects of p-metal contact;108
13.4.1.1;6.4.1.1. p-metallization;108
13.4.1.2;6.4.1.2. Plasma damage;112
13.4.1.3;6.4.1.3. p-InGaAs contact layer thickness;113
13.4.2;6.4.2. Effects of BH interfaces;113
13.4.3;6.4.3. Effects of substrate quality;114
13.5;6.5. Reliability extrapolation and modeling;115
13.5.1;6.5.1. Sublinear model extrapolation;115
13.5.2;6.5.2. Temperature and current accelerations;117
13.6;6.6. Electrostatic discharge (ESD) and electrical overstress (EOS);118
13.6.1;6.6.1. ESD damage characteristics;119
13.6.2;6.6.2. ESD polarity effect;120
13.6.3;6.6.3. ESD soft and hard degradation behaviors;123
13.6.4;6.6.4. Size effect;124
13.6.5;6.6.5. BH versus RWG lasers;126
13.7;6.7. Conclusions;126
13.8;References;127
14;Chapter 7: Reliability of silicon integrated circuits;132
14.1;7.1. Introduction;132
14.2;7.2. Reliability characterization approaches;133
14.3;7.3. Integrated circuit (IC) wear-out failure mechanisms;135
14.3.1;7.3.1. Transistor degradation;135
14.3.1.1;7.3.1.1. Time-dependent dielectric breakdown of gate dielectrics;136
14.3.1.2;7.3.1.2. Bias temperature instabilities;138
14.3.1.2.1;Negative bias temperature instability;138
14.3.1.2.2;Positive bias temperature instability;140
14.3.1.2.3;Impact of BTI on digital circuit reliability;140
14.3.1.3;7.3.1.3. Hot carrier aging;142
14.3.2;7.3.2. Interconnect degradation;142
14.3.2.1;7.3.2.1. Electromigration;143
14.3.2.2;7.3.2.2. Stress voiding;146
14.3.2.3;7.3.2.3. Time-dependent breakdown of interlevel dielectrics;146
14.3.3;7.3.3. SER in Si circuits;148
14.3.3.1;7.3.3.1. Mechanisms and technology trends;148
14.3.3.2;7.3.3.2. Simulation of circuit SER: virtual qualification;150
14.4;7.4. Summary and conclusions;150
14.5;Acknowledgments;152
14.6;References;152
15;Chapter 8: Reliability of emerging nanodevices;160
15.1;8.1. Introduction to emerging nanodevices;160
15.2;8.2. Material and architectural evolution of nanodevices;163
15.3;8.3. Failure mechanisms in nanodevices;165
15.3.1;8.3.1. Front-end failure mechanisms;166
15.3.2;8.3.2. Back-end failure mechanisms;171
15.3.3;8.3.3. Package-level failure mechanisms;174
15.3.4;8.3.4. Failure mechanisms in memory technology;175
15.4;8.4. Reliability challenges: opportunities and issues;177
15.5;8.5. Summary and conclusions;180
15.6;References;180
16;Chapter 9: Design considerations for reliable embedded systems;186
16.1;9.1. Introduction;186
16.2;9.2. Hardware faults;187
16.2.1;9.2.1. Logic faults;187
16.2.2;9.2.2. Timing faults;188
16.2.3;9.2.3. Trends of hardware faults;189
16.3;9.3. Reliable design principles;190
16.3.1;9.3.1. Hardware redundancy;190
16.3.2;9.3.2. Error hardening;192
16.3.3;9.3.3. EDAC codes;193
16.3.4;9.3.4. Re-execution and application checkpointing;194
16.3.5;9.3.5. Industrial practices;195
16.3.6;9.3.6. Design trade-offs;196
16.4;9.4. Low-cost reliable design;197
16.4.1;9.4.1. Microarchitectural approaches;198
16.4.2;9.4.2. System-level approaches;200
16.4.2.1;9.4.2.1. Runtime reliability management;200
16.4.2.2;9.4.2.2. Design-time reliability optimization;201
16.4.3;9.4.3. Software approaches;202
16.5;9.5. Future research directions;204
16.5.1;9.5.1. Cross-layer system adaptation;204
16.5.2;9.5.2. Quality-of-experience-aware design;205
16.5.3;9.5.3. Programming models;206
16.5.4;9.5.4. Reliable design automation;206
16.6;9.6. Conclusions;207
16.7;References;207
17;Chapter 10: Reliability approaches for automotive electronic systems;212
17.1;10.1. Introduction;212
17.2;10.2. Circuit reliability challenges for the automotive industry;212
17.3;10.3. Circuit reliability checking for the automotive industry;213
17.3.1;10.3.1. Voltage-dependent checking;213
17.3.2;10.3.2. Negative voltage checking and reverse current;214
17.3.2.1;10.3.2.1. Schematic;214
17.3.2.2;10.3.2.2. Layout;214
17.3.3;10.3.3. ESD and latch-up verification;215
17.3.4;10.3.4. EOS susceptibility;215
17.4;10.4. Using advanced electronic design automation (EDA) tools;217
17.4.1;10.4.1. Voltage propagation;218
17.4.2;10.4.2. Circuit recognition;218
17.4.3;10.4.3. Current density and point-to-point checking;219
17.4.4;10.4.4. Topology-aware geometric checking;221
17.4.5;10.4.5. Voltage-dependent DRC;222
17.5;10.5. Case studies and examples;225
17.5.1;10.5.1. Case study 1;225
17.5.2;10.5.2. Case study 2;226
17.5.3;10.5.3. Case study 3;228
17.6;10.6. Conclusion;229
17.7;Acknowledgment;229
17.8;References;229
18;Chapter 11: Reliability modeling and accelerated life testing for solar power generation systems;232
18.1;11.1. Introduction;232
18.2;11.2. Overview;232
18.2.1;11.2.1. Brief overview of solar power generation systems;233
18.2.2;11.2.2. Overview of the chapter;235
18.3;11.3. Challenges;235
18.3.1;11.3.1. Failures;236
18.3.2;11.3.2. Bankability;237
18.3.3;11.3.3. Product testing;237
18.4;11.4. Modeling;239
18.5;11.5. Accelerated life testing (ALT);243
18.5.1;11.5.1. Time compression;244
18.5.2;11.5.2. Using three stresses to create a model;244
18.5.3;11.5.3. Using an existing model;245
18.5.3.1;11.5.3.1. Expected failure mechanisms and lifetime data;246
18.5.3.2;11.5.3.2. Reliability calculations;246
18.5.3.2.1;IGBT reliability calculations;250
18.5.4;11.5.4. Modeling reliability and availability;251
18.5.4.1;11.5.4.1. Vendor data reliability calculation example;252
18.5.5;11.5.5. Using ALT;254
18.6;11.6. ALT example: how to craft a thermal cycling ALT plan for SnAgCu (SAC) solder failure mechanism;255
18.6.1;11.6.1. Objective;255
18.6.2;11.6.2. ALT plan summary;255
18.6.3;11.6.3. Background;255
18.6.4;11.6.4. ALT approach;256
18.6.5;11.6.5. Thermal cycling ALT plan details;256
18.6.6;11.6.6. Environmental conditions;256
18.6.6.1;11.6.6.1. Measured temperature rise;256
18.6.6.2;11.6.6.2. Climatic data;256
18.6.6.3;11.6.6.3. Product A average daily thermal range;257
18.6.6.4;11.6.6.4. Product B average daily thermal range;257
18.6.7;11.6.7. Temperatures;257
18.6.8;11.6.8. Dwell times;257
18.6.9;11.6.9. Acceleration factor determination;257
18.6.9.1;11.6.9.1. Product A acceleration factor;257
18.6.9.2;11.6.9.2. Product B acceleration factor;258
18.6.10;11.6.10. Sample-size determination;258
18.6.10.1;11.6.10.1. Product A sample size;259
18.6.10.2;11.6.10.2. Product B sample size;259
18.6.11;11.6.11. Assumptions;259
18.7;11.7. How to craft a temperature, humidity, and bias ALT plan for CMOS metallization corrosion;260
18.7.1;11.7.1. Objective;260
18.7.2;11.7.2. ALT plan summary;260
18.7.3;11.7.3. Background;260
18.7.4;11.7.4. ALT approach;260
18.7.5;11.7.5. THB ALT plan details;261
18.7.6;11.7.6. Environmental conditions;261
18.7.6.1;11.7.6.1. Measured temperature rise;261
18.7.6.2;11.7.6.2. Climatic data;261
18.7.6.3;11.7.6.3. Product A average daily thermal range;262
18.7.6.4;11.7.6.4. Product B average daily thermal range;262
18.7.7;11.7.7. Acceleration factor determination;262
18.7.7.1;11.7.7.1. Product A acceleration factor;262
18.7.7.2;11.7.7.2. Product B acceleration factor;263
18.7.8;11.7.8. Sample-size determination;263
18.7.8.1;11.7.8.1. Product A sample size;263
18.7.8.2;11.7.8.2. Product B sample size;263
18.7.9;11.7.9. Assumptions;264
18.8;11.8. Developments and opportunities;264
18.9;11.9. Conclusions;265
18.10;11.10. Sources of further information;265
18.11;References;265
19;Index;268

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