Stringham MSEE / Stringham Hardware/Firmware Interface Design

Best Practices for Improving Embedded Systems Development
1. Auflage 2009
ISBN: 978-0-08-088019-8
Verlag: Elsevier Science & Techn.
Format: EPUB
Kopierschutz: 6 - ePub Watermark

E-Book, Englisch, 376 Seiten

Why care about hardware/firmware interaction? These interfaces are critical, a solid hardware design married with adaptive firmware can access all the capabilities of an application and overcome limitations caused by poor communication. For the first time, a book has come along that will help hardware engineers and firmware engineers work together to mitigate or eliminate problems that occur when hardware and firmware are not optimally compatible. Solving these issues will save time and money, getting products to market sooner to create more revenue.
The principles and best practices presented in this book will prove to be a valuable resource for both hardware and firmware engineers. Topics include register layout, interrupts, timing and performance, aborts, and errors. Real world cases studies will help to solidify the principles and best practicies with an aim towards cleaner designs, shorter schedules, and better implementation!
Reduce product development delays with the best practices in this bookConcepts apply to ASICs, ASSPs, SoCs, and FPGAsReal-world examples and case studies highlight the good and bad of design processes

Autoren/Hrsg.

Stringham MSEE, Gary

Stringham, Gary

Inhaltsverzeichnis

1;Front Cover;1
2;Title Page;2
3;Copyright Page;3
4;Table of Contents;4
5;Preface;11
6;Chapter 1: Introduction;18
6.1;1.1. What Is the Hardware/Firmware Interface?;19
6.1.1;1.1.1. What Are Hardware, Chips, and Blocks?;19
6.1.2;1.1.2. What Are Firmware and Device Drivers?;23
6.2;1.2. What Is a Best Practice?;24
6.2.1;1.2.1. What Is a Principle?;26
6.2.2;1.2.2. Benefits of Principles and Practices;27
6.3;1.3. “First Time Right” Also Means …;27
6.3.1;1.3.1. Easier to Program;28
6.3.2;1.3.2. Easier to Debug;28
6.3.3;1.3.3. Easier to Work around Defects;29
6.4;1.4. Target Audience;30
6.4.1;1.4.1. Hardware Engineers;30
6.4.2;1.4.2. Firmware Engineers;30
6.4.3;1.4.3. This Book in a University Setting;31
6.5;1.5. Project Life Cycle;31
6.6;1.6. Case Study;32
6.6.1;1.6.1. Monochrome Video Block in the Unity ASIC;32
6.6.2;1.6.2. A Case Study of a Good Example?;34
6.7;1.7. Summary;34
6.8;References;35
7;Chapter 2: Principles;36
7.1;2.1. Seven Principles of Hardware/Firmware Interface Design;36
7.1.1;2.1.1. Collaborate on the Design;37
7.1.2;2.1.2. Set and Adhere to Standards;38
7.1.3;2.1.3. Balance the Load;40
7.1.4;2.1.4. Design for Compatibility;42
7.1.5;2.1.5. Anticipate the Impacts;43
7.1.6;2.1.6. Design for Contingencies;44
7.1.7;2.1.7. Plan Ahead;46
7.2;2.2. Summary;47
8;Chapter 3: Collaboration;48
8.1;3.1. First Steps;48
8.1.1;3.1.1. Roles;48
8.1.2;3.1.2. Kick-off Activities;51
8.2;3.2. Formal Collaboration;52
8.2.1;3.2.1. Regular Meetings;52
8.2.2;3.2.2. Initial Firmware Support;54
8.2.3;3.2.3. Co-Development Techniques;55
8.2.4;3.2.4. End-Game Hardware Support;57
8.2.5;3.2.5. Documentation;58
8.3;3.3. Informal Collaboration;61
8.3.1;3.3.1. Formal Organizational Structure;61
8.3.2;3.3.2. Hardware Engineers’ Initiative;62
8.3.3;3.3.3. Firmware Engineers’ Initiative;63
8.3.4;3.3.4. Collaborative Problem Solving;64
8.4;3.4. Summary;65
8.4.1;3.4.1. Supporting Principles;66
8.5;References;66
9;Chapter 4: Planning;68
9.1;4.1. Industry Standards;68
9.1.1;4.1.1. Existing Standards;69
9.1.2;4.1.2. Implementing the Standard;70
9.1.3;4.1.3. Derivations or New Creations;72
9.2;4.2. Common Version;73
9.3;4.3. Compatibility;75
9.3.1;4.3.1. Range of Backward and Forward Compatibility;76
9.3.2;4.3.2. Combinations of Old vs. New;77
9.4;4.4. Defects;78
9.4.1;4.4.1. Document Defects;78
9.4.2;4.4.2. Fix Defects;80
9.4.3;4.4.3. Test Plan to Look for Defects;82
9.5;4.5. Analysis;83
9.5.1;4.5.1. Shared Pins;83
9.5.2;4.5.2. Buffer Management;84
9.5.3;4.5.3. Hardware/Firmware Interactions;84
9.5.4;4.5.4. Analyzing Third-Party IP;86
9.6;4.6. Postmortem;87
9.7;4.7. Summary;88
9.7.1;4.7.1. Supporting Principles;89
10;Chapter 5: Documentation;90
10.1;5.1. Types;91
10.1.1;5.1.1. Level and Types of Documentation;91
10.1.2;5.1.2. Chip-Level vs.Block-Level Documentation;92
10.1.3;5.1.3. Supported vs. Unsupported Documentation;94
10.2;5.2. Document Management;96
10.2.1;5.2.1. Document Standards;96
10.2.2;5.2.2. When to Write;97
10.2.3;5.2.3. Accuracy;98
10.3;5.3. Reviews;100
10.3.1;5.3.1. When to Review;100
10.3.2;5.3.2. Tracking Documentation Changes;101
10.3.3;5.3.3. Firmware Engineers’ Responsibilities Regarding Reviews;102
10.4;5.4. Content;104
10.4.1;5.4.1. General Content;104
10.4.2;5.4.2. Sample Document Template;105
10.4.3;5.4.3. History;106
10.4.4;5.4.4. Features and Assumptions;108
10.4.5;5.4.5. Reference and Tutorial;109
10.4.6;5.4.6. Glossary and Errata;111
10.5;5.5. Registers;112
10.5.1;5.5.1. Document Registers;112
10.5.2;5.5.2. Register Design Tools;113
10.5.3;5.5.3. Table of Registers;117
10.5.4;5.5.4. Register Details and Description;118
10.6;5.6. Bits;120
10.6.1;5.6.1. Register Map Format;120
10.6.2;5.6.2. Bit Positions, Types, and Defaults;121
10.6.3;5.6.3. Bit Descriptions;123
10.6.4;5.6.4. Abort Impact;123
10.6.5;5.6.5. Test and Debug Bits;124
10.7;5.7. Interrupts;125
10.7.1;5.7.1. Edge- vs. Level-Triggered;125
10.7.2;5.7.2. Enabling and Acknowledging Interrupts;126
10.7.3;5.7.3. Interrupts Not Quite Done;127
10.7.4;5.7.4. Interrupts Repeating without Intervention;127
10.8;5.8. Time;128
10.8.1;5.8.1. Ranges of Time;128
10.8.2;5.8.2. Unit of Time;130
10.9;5.9. Errors;131
10.9.1;5.9.1. Two Types of Errors;132
10.9.2;5.9.2. Copious Information about the Errors;133
10.9.3;5.9.3. State of the Block after an Error;134
10.9.4;5.9.4. Firmware Steps to Recover;135
10.10;5.10. Information;136
10.10.1;5.10.1. Illegal Configuration;136
10.10.2;5.10.2. State Machines;136
10.10.3;5.10.3. How to Abort;137
10.11;5.11. Summary;138
10.11.1;5.11.1. Supporting Principles;139
11;Chapter 6: Superblock;140
11.1;6.1. Benefits of a Superblock;140
11.1.1;6.1.1. The Block’s Entourage;141
11.1.2;6.1.2. Reasons for Having Unused Logic;141
11.1.3;6.1.3. Reasons against Having Unused Logic;146
11.2;6.2. Consolidation;148
11.2.1;6.2.1. Make a Superblock;148
11.2.2;6.2.2. Make a Supermodule;150
11.2.3;6.2.3. Evolutionary Design;150
11.2.4;6.2.4. Add Future Features;152
11.2.5;6.2.5. Superblock Version Number;154
11.3;6.3. I/O Signals;154
11.4;6.4. Parameterization;156
11.4.1;6.4.1. Reducing the Silicon Space;156
11.4.2;6.4.2. Minimizing Parameterization Risks;157
11.4.3;6.4.3. Parameterization Information for Firmware;159
11.4.4;6.4.4. Optional vs. Fixed Registers and Bits;162
11.5;6.5. Summary;163
11.5.1;6.5.1. Supporting Principles;164
11.6;Reference;164
12;Chapter 7: Design;166
12.1;7.1. Event Notification;166
12.1.1;7.1.1. No Indication;167
12.1.2;7.1.2. Timed Delay;168
12.1.3;7.1.3. Status Bit;170
12.1.4;7.1.4. Interrupts;172
12.2;7.2. Performance;174
12.2.1;7.2.1. Increasing the Buffer;175
12.2.2;7.2.2. Working Ahead;176
12.2.3;7.2.3. Tuning;177
12.2.4;7.2.4. Margins;178
12.3;7.3. Power-On;178
12.3.1;7.3.1. Power-On Interaction;178
12.3.2;7.3.2. Power-On State of I/O Lines;180
12.3.3;7.3.3. Block-Level Power Control;180
12.4;7.4. Communication and Control;181
12.4.1;7.4.1. Error Information;181
12.4.2;7.4.2. DMA Features;181
12.4.3;7.4.3. Sharing I/O Pins;183
12.4.4;7.4.4. Hiding Implementation Details;184
12.5;7.5. Summary;186
12.5.1;7.5.1. Supporting Principles;187
13;Chapter 8: Registers;188
13.1;8.1. Addressing;189
13.1.1;8.1.1. Processor Access;189
13.1.2;8.1.2. Chip Base Addresses;192
13.1.3;8.1.3. Block Offset and Base Addresses;193
13.1.4;8.1.4. Register Offset Addresses;195
13.1.5;8.1.5. Sub-Blocks;196
13.1.6;8.1.6. Bursting;196
13.1.7;8.1.7. Unused Address Locations;197
13.1.8;8.1.8. Changes in the Next Chip;198
13.2;8.2. Bit Assignment;200
13.2.1;8.2.1. Assigning Bit Positions;200
13.2.2;8.2.2. Multi-Bit Fields;202
13.2.3;8.2.3. Multi-Register Fields;204
13.2.4;8.2.4. Unused Bit Positions;205
13.2.5;8.2.5. Changes in the Next Revision;206
13.2.6;8.2.6. Bit Types;209
13.2.7;8.2.7. Bit Types in Registers;212
13.2.8;8.2.8. Grouping by Operational Mode;214
13.2.9;8.2.9. Multiple Instantiations of a Block;215
13.3;8.3. Data Types;216
13.3.1;8.3.1. Integers;217
13.3.2;8.3.2. Real Numbers;218
13.3.3;8.3.3. Pointers;222
13.3.4;8.3.4. Constants;224
13.4;8.4. Hardware Identification;224
13.4.1;8.4.1. Chip ID and Version;225
13.4.2;8.4.2. Block ID and Version;226
13.5;8.5. Communication and Control;227
13.5.1;8.5.1. Necessary Information;227
13.5.2;8.5.2. Queuing Tasks in the Block;228
13.5.3;8.5.3. Coherent Register Contents;233
13.5.4;8.5.4. Atomic Register Access;234
13.6;8.6. Summary;238
13.6.1;8.6.1. Supporting Principles;239
14;Chapter 9: Interrupts;240
14.1;9.1. Design;241
14.1.1;9.1.1. An Interrupt Supermodule;241
14.1.2;9.1.2. Hierarchical Interrupt Structure;243
14.1.3;9.1.3. Interrupt Sharing;245
14.1.4;9.1.4. Source Signal Integrity;247
14.1.5;9.1.5. Types of Interrupt Triggers;248
14.2;9.2. Pending Register;253
14.2.1;9.2.1. Acknowledging an Interrupt;253
14.2.2;9.2.2. Order of Interrupt Positions;256
14.3;9.3. Enable Register;257
14.3.1;9.3.1. A 1 Enables the Interrupt;258
14.3.2;9.3.2. Enable Controls Interrupt;258
14.3.3;9.3.3. Default Settings for Enable;260
14.4;9.4. Optional Registers;260
14.4.1;9.4.1. Source Status Register;260
14.4.2;9.4.2. Post Register;262
14.4.3;9.4.3. Atomic Enable/Disable Registers;262
14.4.4;9.4.4. Masked Register;263
14.4.5;9.4.5. Instantiation Register;263
14.4.6;9.4.6. Addresses of Optional Registers;264
14.5;9.5. Interrupt Module Review;265
14.5.1;9.5.1. Interrupt Channels;266
14.5.2;9.5.2. Interrupt Module;268
14.5.3;9.5.3. External Connections;269
14.6;9.6. Triggering on Both Edges;270
14.6.1;9.6.1. Use Two Interrupt Channels;270
14.6.2;9.6.2. Channel Positions of Leading and Trailing Interrupts;272
14.7;9.7. Using the Interrupt Module;274
14.7.1;9.7.1. When to Allocate an Interrupt Channel;274
14.7.2;9.7.2. Repeated Interrupts;276
14.7.3;9.7.3. Address Mapping;276
14.8;9.8. Summary;277
14.8.1;9.8.1. Supporting Principles;278
15;Chapter 10: Aborts, etc.;280
15.1;10.1. Definitions;280
15.2;10.2. Halts;282
15.3;10.3. Resets;283
15.4;10.4. Aborts;285
15.4.1;10.4.1. The Need for Aborts;285
15.4.2;10.4.2. Firmware’s Interaction with Aborts;287
15.4.3;10.4.3. Abort Behavior;289
15.4.4;10.4.4. Abort Interactions between Blocks;291
15.5;10.5. Summary;292
15.5.1;10.5.1. Supporting Principles;293
16;Chapter 11: Hooks;294
16.1;11.1. Designing for Hooks;295
16.1.1;11.1.1. What Hooks to Add;296
16.1.2;11.1.2. Adding Registers;296
16.1.3;11.1.3. Looking for Potential Problem Areas;297
16.1.4;11.1.4. Removing Workarounds;297
16.2;11.2. Peek…;298
16.2.1;11.2.1. Internal Registers;298
16.2.2;11.2.2. Signals;299
16.2.3;11.2.3. Memory;300
16.2.4;11.2.4. State Machines;302
16.3;11.3. …And Poke;304
16.3.1;11.3.1. Destructive Reads and Writes;304
16.3.2;11.3.2. Input and Output Signals;305
16.3.3;11.3.3. Overwriting Registers;306
16.4;11.4. Monitor;306
16.4.1;11.4.1. Event Tracking;306
16.4.2;11.4.2. Timers;308
16.4.3;11.4.3. Data Watching;309
16.5;11.5. More Hooks;310
16.5.1;11.5.1. Bypass Paths;310
16.5.2;11.5.2. Extra Resources for Test and Debug;312
16.5.3;11.5.3. Dedicated Processor;314
16.6;11.6. Summary;315
16.6.1;11.6.1. Supporting Principles;316
17;Chapter 12: Conclusion;318
17.1;12.1. Key Points;318
17.2;12.2. Benefits;319
17.3;12.3. Seven Principles of Hardware/Firmware Interface Design;319
17.4;12.4. It Finally Works! Let’s Ship It!;320
18;Appendix A: Best Practices;324
19;Appendix B: Bicycle Controller Specification;344
20;Appendix D: Glossary;362
21;Index;366