Staunstrup A Formal Approach to Hardware Design

Erscheinungsjahr 2012
ISBN: 978-1-4615-2764-0
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 253, 232 Seiten, eBook

Reihe: The Springer International Series in Engineering and Computer Science

A Formal Approach to Hardware Design discusses designing computations to be realised by application specific hardware. It introduces a formal design approach based on a high-level design language called Synchronized Transitions. The models created using Synchronized Transitions enable the designer to perform different kinds of analysis and verification based on descriptions in a single language. It is, for example, possible to use exactly the same design description both for mechanically supported verification and synthesis. Synchronized Transitions is supported by a collection of public domain CAD tools. These tools can be used with the book in presenting a course on the subject. A Formal Approach to Hardware Design illustrates the benefits to be gained from adopting such techniques, but it does so without assuming prior knowledge of formal design methods. The book is thus not only an excellent reference, it is also suitable for use by students and practitioners.

Zielgruppe

Research

Autoren/Hrsg.

Staunstrup, Jørgen

Inhaltsverzeichnis

1 Formal Design Methods.- 1.1 Why Use Formal Methods?.- 1.2 Models of Integrated Circuits.- 1.3 Synchronized Transitions.- 1.4 Background.- 2 DESIGNING WITH TRANSITIONS.- 2.1 Computational Model.- 2.2 States.- 2.3 Transitions.- 2.4 Arrays and Quantification.- 2.5 Fixed Points.- 2.6 Statics.- 2.7 Named Transitions.- 2.8 Cells.- 2.9 Conditional Instantiation.- 2.10 Restricting State Variables.- 2.11 Other Constructs.- 2.12 Background.- 2.13 Exercises.- 3 Formal Verification.- 3.1 Invariants and Protocols.- 3.2 Verification of Invariants and Protocols.- 3.3 Mechanical Verification.- 3.4 Verification of Modular Designs.- 3.5 Background.- 3.6 Exercises.- 4 Synchronous Designs.- 4.1 The Synchronous Combinator.- 4.2 Verification of Synchronous Designs.- 4.3 A Fast Adder.- 4.4 Background.- 4.5 Exercises.- 5 Synchronous Realizations.- 5.1 Two-phase Realizations.- 5.2 Timing Estimation.- 5.3 Asynchronous Designs.- 5.4 Implementation Conditions.- 5.5 Background.- 5.6 Exercises.- 6 Refinement.- 6.1 Abstraction Functions.- 6.2 The Weak Refinement Condition.- 6.3 Mechanization.- 6.4 Interface Refinement.- 6.5 Background.- 6.6 Exercises.- 7 Self-Timed Circuits.- 7.1 Classification.- 7.2 Models of Self-timed Circuits.- 7.3 Speed-independence.- 7.4 Hierarchical Designs.- 7.5 Delay-insensitivity.- 7.6 Background.- 7.7 Exercises.- 8 Towards Larger Designs.- 8.1 Combining Asynchronous and Synchronous Computations.- 8.2 Codesign.- 8.3 Background.- 9 EPILOG.- A Synchronized Transitions Report.- References.