Hardware Architectures for Post-Quantum Digital Signature Schemes

1. Auflage 2021
ISBN: 978-3-030-57681-3
Verlag: Springer International Publishing

Buch, Englisch, 170 Seiten, Format (B × H): 160 mm x 241 mm, Gewicht: 459 g

This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification.  The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs.

• Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;
• Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;
• Enables designers to build hardware implementations that are resilient to a variety of side-channels.

Zielgruppe

Research

Autoren/Hrsg.

Soni, Deepraj

Basu, Kanad

Karri, Ramesh

Nabeel, Mohammed

Aaraj, Najwa

Manzano, Marc

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Technische Wissenschaften Energietechnik | Elektrotechnik Elektrotechnik
• Mathematik | Informatik EDV | Informatik Informatik Mensch-Maschine-Interaktion Ambient Intelligence, RFID, Internet der Dinge
• Technische Wissenschaften Elektronik | Nachrichtentechnik Nachrichten- und Kommunikationstechnik
• Mathematik | Informatik EDV | Informatik Informatik Rechnerarchitektur

Inhaltsverzeichnis

Introduction.- qTESLA.- CRYSTALS –Dilithium.- MQDSS.- SPHINCS.- Luov.- Falcon.- Picnic.- GeMSS.- Power, Performance, Area, and Security (PPAS) Comparison of the PQC Algorithms.- Conclusions.

Über Autor(innen)

Deepraj Soni is a Ph.D. student at NYU Tandon School of Engineering. Deepraj works on hardware implementation, evaluation and security of post quantum cryptographic algorithms. He received his M.Tech from the Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT B). His thesis focused on developing a framework for hardware software co simulator and neural network implementation on an FPGA. After graduation, Deepraj worked as a design engineer in the semiconductor division of Samsung and SanDisk. At Samsung, he was responsible for the design and architecture of the image processing IPs such as region segmentation and Embedded CODEC. He was also responsible for communication IPs such as FFT/IFFT, Time & Frequency Deinterleaving and Demapper for canceling the noise. At SanDisk, Deepraj helped in the development of System On Chip (SoC) level design for the memory controller.