Sin / U / Martins Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters

1. Auflage 2010
ISBN: 978-90-481-9710-1
Verlag: Springer Netherlands
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 150 Seiten

Reihe: Analog Circuits and Signal Processing

Analog-to-Digital Converters (ADCs) play an important role in most modern signal processing and wireless communication systems where extensive signal manipulation is necessary to be performed by complicated digital signal processing (DSP) circuitry. This trend also creates the possibility of fabricating all functional blocks of a system in a single chip (System On Chip - SoC), with great reductions in cost, chip area and power consumption. However, this tendency places an increasing challenge, in terms of speed, resolution, power consumption, and noise performance, in the design of the front-end ADC which is usually the bottleneck of the whole system, especially under the unavoidable low supply-voltage imposed by technology scaling, as well as the requirement of battery operated portable devices. Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters will present new techniques tailored for low-voltage and high-speed Switched-Capacitor (SC) ADC with various design-specific considerations.

Dr. Sin is currently the Secretary of IEEE Solid-State Circuit Society (SSCS) Macau Chapter, and Treasurer/Secretary of IEEE Macau CAS/COM Joint Chapter and the Member of Executive Committee - Academic Affair of IEEE Macau, and has been the member of Technical Program and Organization Committee of the 2004 IEEJ AVLSI Workshop, Technical Session Chair of 2006 RIUPEEEC Conference, as well as the Special Session Co-Chair and Technical Program Committee Member of 2008 IEEE APCCAS Conference, Referee of IEEE Transaction of Instrumentation and Measurement and IEEE ISCAS Conference. He received the Chipidea Microelectronics Prize - Postgraduate Level in 2008 for outstanding Academic and Research achievements in Microelectronics, as well as the Financial Support Award for Student Paper Contest in 2005 International Symposium on Circuits and Systems (ISCAS) held in Kobe, Japan, the Paper with Certificate of Merit for the 2006 RIUPEEEC Conference, as well as Award of Dean Honor List, Faculty of Science and Technology, University of Macau, in 1999-2000 and 2000-2001 respectively. Dr. U is currently Senior Member of IEEE, the Industrial Relationship Officer of IEEE Macau Section and the Chairman of IEEE Macau CAS/COMM and SSC chapters. He has been with technical review committee of various IEEE journals and conferences. He was the chairman of the local organization committee of IEEJ AVLSIWS'04, Technical Program co-Chair of IEEE APCCAS'08. He is also the Program Co-chair of ICICS'09 and Technical Program Committee of ASSCC. Prof. Rui Martins is an IEEE Fellow, was the Founding Chairman of the IEEE Macau Section from 2003 to 2005, and of the IEEE Macau Joint-Chapter on Circuits And Systems (CAS) / Communications (COM) from 2005 to 2008 [World Chapter of the Year 2009 of the IEEE Circuits And Systems Society (CASS)]. He was the General Chair of the 2008 IEEE Asia-Pacific Conference on Circuits And Systems - APCCAS'2008, and was elected Vice-President for the Region 10 (Asia, Australia, the Pacific) of the IEEE Circuits And Systems Society (CASS), for the period of 2009 to 2010. He is Associate Editor of the IEEE Transactions on Circuits and Systems II - Express Briefs,for the period of 2010 to 2011. He was the recipient of 2 government decorations: the Medal of Professional Merit from Macao Government (Portuguese Administration) in 1999, and the Honorary Title of Value from Macao SAR Government (Chinese Administration) in 2001.

Autoren/Hrsg.

Sin, Sai-Weng

U, Seng-Pan

Martins, Rui Paulo

Inhaltsverzeichnis

1;Preface;8
2;Acknowledgement;10
3;Contents;12
4;Abbreviations;16
5;Chapter 1: Introduction;18
5.1;1.1 Low-Voltage High-Speed Analog-to-Digital Conversion;18
5.2;1.2 Applications of High-Speed ADCs;20
5.3;1.3 Deep-Submicron CMOS ADCs Designs;22
5.4;1.4 Main Objective and Design Challenges;24
5.5;References;25
6;Chapter 2: Challenges in Low-Voltage Circuit Designs;28
6.1;2.1 Introduction;28
6.2;2.2 The Impact of CMOS Technology Scaling;28
6.3;2.3 Design Challenges: Intrinsic Performance Degradation;30
6.3.1;2.3.1 Transconductance Degradation;30
6.3.2;2.3.2 Output Resistance Degradation;31
6.3.3;2.3.3 Trends of Unity-Gain Frequency in Technology Scaling;32
6.4;2.4 Circuit Level Design Challenges: Opamps;32
6.5;2.5 Circuit Level Design Challenges: Switches;34
6.5.1;2.5.1 Switch Positioning;36
6.5.2;2.5.2 Clock Boosting;36
6.5.3;2.5.3 Bootstrapped Switches;37
6.5.4;2.5.4 Switched-Op38
6.5.5;2.5.5 Reset-Op39
6.5.6;2.5.6 Switched-RC Techniques;40
6.6;2.6 Summary;41
6.7;References;42
7;Chapter 3: Advanced Low Voltage Circuit Techniques;44
7.1;3.1 Introduction;44
7.2;3.2 Virtual-Ground Common-Mode Feedback and Output Common-Mode Error Correction;45
7.2.1;3.2.1 Low-Voltage CMFB Design Challenges;45
7.2.2;3.2.2 Novel Virtual Ground CMFB Technique;46
7.2.3;3.2.3 Practical Implementation of VG-CMFB;48
7.2.4;3.2.4 Output Common-Mode Error Correction;49
7.3;3.3 Cross-Coupled Passive Sampling Interface;50
7.3.1;3.3.1 Problems in Existing Solutions;50
7.3.2;3.3.2 Cross-Coupled Passive Sampling Interface;52
7.4;3.4 Voltage-Controlled Level Shifting;56
7.5;3.5 Feedback Current Biasing Technique;57
7.6;3.6 Low-Voltage Finite-Gain-Compensation;60
7.6.1;3.6.1 The Need for Finite-Gain Compensation;60
7.6.2;3.6.2 Auxiliary Differential-Difference Amplifier;64
7.7;3.7 Low-Voltage Offset-Compensation;66
7.7.1;3.7.1 The Crossed-Coupled S/H;66
7.7.2;3.7.2 The SC Amplifier;68
7.8;3.8 Summary;69
7.9;References;70
8;Chapter 4: Time-Interleaving: Multiplying the Speed of the ADC;72
8.1;4.1 Introduction;72
8.2;4.2 Time-Interleaved ADC Architecture;72
8.3;4.3 Channel Mismatch Analysis;74
8.4;4.4 Offset Mismatch;78
8.5;4.5 Gain Mismatch;80
8.6;4.6 Timing Mismatch;83
8.7;4.7 Bandwidth Mismatch;85
8.8;4.8 Summary;89
8.9;References;90
9;Chapter 5: Design of a 1.2 V, 10-bit, 60-360 MHz Time-Interleaved Pipelined ADC;92
9.1;5.1 Introduction;92
9.2;5.2 The Overall ADC Architecture;93
9.3;5.3 Prototype Circuit-Level Design;94
9.3.1;5.3.1 Resistively Demultiplexed Front-End Sample-and-Hold;94
9.3.2;5.3.2 1.5 b/Stage Multiplying-Digital-to-Analog-Converter (MDAC);95
9.3.3;5.3.3 Current-Mode Sub-ADC Design;97
9.3.4;5.3.4 Programmable Timing-Skew Insensitive Clock Generator;98
9.3.5;5.3.5 Noise Analysis;99
9.3.6;5.3.6 Channel Mismatch Analysis;102
9.4;5.4 Layout Considerations;103
9.5;5.5 Simulation Results;105
9.5.1;5.5.1 Opamp Simulations;105
9.5.2;5.5.2 Front-End S/H;105
9.5.3;5.5.3 Current-Mode Comparator;107
9.5.4;5.5.4 The Overall ADC Simulations;109
9.6;5.6 Summary;111
9.7;References;111
10;Chapter 6: Experimental Results;113
10.1;6.1 Introduction;113
10.2;6.2 The Prototype PCB Design;113
10.2.1;6.2.1 The Floor Plan;113
10.2.2;6.2.2 Power Supply Considerations;114
10.2.3;6.2.3 Signal Trace Routing;116
10.3;6.3 Measurement Setup and Results;116
10.3.1;6.3.1 Time-Domain Digital Output Code Pattern;118
10.3.2;6.3.2 Static Performance;118
10.3.3;6.3.3 Dynamic Performance;120
10.4;6.4 Summary;124
10.5;References;127
11;Chapter 7: Conclusions and Prospective for Future Work;129
11.1;7.1 Conclusions;129
11.2;7.2 Prospective for Future Work;130
11.2.1;7.2.1 Low-Noise and Low-Voltage Circuit Techniques Implementation;131
11.2.2;7.2.2 Fully Dynamic ADC Implementations;131
11.2.3;7.2.3 SC Circuits Implemented with Open-Loop Amplifiers;131
11.2.4;7.2.4 Digital Calibration;132
11.3;References;132
12;Appendix A Operating Principle of VG-CMFB with O-CMEC;133
13;Appendix B Mathematical Analysis of Bandwidth Mismatches;136
14;Appendix C Noise Analysis of Advanced Reset-Opamp Circuits;140
15;Appendix D Special Case in Gain Mismatch;145
16;Index;146