Low Power Networks-On-Chip

2011
ISBN: 978-1-4419-6910-1
Verlag: Springer Us

Buch, Englisch, 287 Seiten, Format (B × H): 167 mm x 244 mm, Gewicht: 1340 g

In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.

Zielgruppe

Research

Autoren/Hrsg.

Silvano, Cristina

Lajolo, Marcello

Palermo, Gianluca

Fachgebiete

• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

Network-on-Chip Power Estimation.- Timing.- synchronous/asynchronous communication.- Network-on-Chip link design.- Topology exploration.- Network-on-Chip support for CMP/MPSoCs.- Network design for 3D stacked logic and memory.- Beyond the wired Network-on-Chip.