CMOS PLL Synthesizers: Analysis and Design

1. Auflage. Softcover version of original hardcover Auflage 2005
ISBN: 978-1-4419-3650-9
Verlag: Springer US

Buch, Englisch, 216 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 359 g

Reihe: The Springer International Series in Engineering and Computer Science

This book presents both fundamentals and the state of the art of PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, Sigma Delta fractional-N synthesizer prototype is implemented in 0.35m m CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which tackle speed and integration bottlenecks of PLL synthesizer elegantly. This book is conceived as a PLL synthesizer manual for both academia researchers and industry design engineers.

Zielgruppe

Research

Autoren/Hrsg.

Sanchez-Sinencio, Edgar

Shu, Keliu

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Halb- und Supraleitertechnologie
• Mathematik | Informatik EDV | Informatik Technische Informatik Externe Speicher & Peripheriegeräte

Inhaltsverzeichnis

Frequency Synthesizer for Wireless Applications.- PLL Frequency Synthesizer.- ?? Fractional-N PLL Synthesizer.- Enhanced Phase Switching Prescaler.- Loop Filter with Capacitance Multiplier.- Other Building Blocks of PLL.- Prototype Measurement Results.- Conclusions.