Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications

1. Auflage. Softcover version of original hardcover Auflage 2006
ISBN: 978-1-4419-3977-7
Verlag: Springer US

Buch, Englisch, 411 Seiten, Paperback, Format (B × H): 160 mm x 240 mm, Gewicht: 680 g

The most important issue confronting CMOS technology is the power explosion of chips arising from the scaling law. Fully-depleted (FD) SOI technology provides a promising low-power solution to chip implementation. Ultralow-power VLSIs, which have a power consumption of less than 10 mW, will be key components of terminals in the coming ubiquitous-IT society. Fully-depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications addresses the problem of reducing the supply voltage of conventional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit design for FD-SOI devices at a supply voltage of 0.5 V. The topics include the minimum required knowledge of the fabrication of SOI substrates; FD-SOI devices and the latest developments in device and process technologies; and ultralow-voltage circuits, such as digital circuits, analog/RF circuits, and DC-DC converters. Each ultra-low-power technique related to devices and circuits is fully explained using figures to help understanding.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Sakurai, Takayasu

Douseki, Takakuni

Matsuzawa, Akira

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Mathematik | Informatik EDV | Informatik Technische Informatik Externe Speicher & Peripheriegeräte
• Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
• Mathematik | Informatik EDV | Informatik Technische Informatik Hardware: Grundlagen und Allgemeines
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Geisteswissenschaften Design Produktdesign, Industriedesign

Inhaltsverzeichnis

FD-SOI Device and Process Technologies.- Ultralow-Power Circuit Design with FD-SOI Devices.- 0.5-V MTCMOS/SOI Digital Circuits.- 0.5-1V MTCMOS/SOI Analog/RF Circuits.- SPICE Model for SOI MOSFETs.- Applications.- Prospects for FD-SOI Technology.

Über Autor(innen)

Takayasu Sakurai received the Ph.D degree in Electronic Engineering from University of Tokyo, Japan, in 1981 and he joined Toshiba Corporation, where he designed CMOS DRAM, SRAM, BiCMOS ASIC's, RISC's, and multimedia VLSI's. He worked on simple yet accurate interconnect delay, capacitance and MOS models widely used as alpha power-law MOS model. He proposed to sense-amplifying flip-flops, variable threshold voltage CMOS scheme, dual voltage converter scheme, hot carrier resilient circuits and other numerous digital and memory circuits, which are adopted in current high-performance, low-power VLSI's. He was a visiting researcher at University of California, Berkeley from 1988 to 1990. In 1996, he moved to University of Tokyo and is consulting to US startup companies. He has published about 250 technical publications including more than 30 invited papers and 6 books and filed about 100 patents. He is a recipient of four product awards and two design contest awards. He served as a conference chair for the Symposium on VLSI Circuits, and a technical program committee member for ISSCC, CICC, DAC, ICCAD, FPGA workshop, ISLPED, ASPDAC, TAU, and other international conferences. He is a keynote speaker for the 2003 ISSCC. He is an IEEE Fellow, an elected Administration Committee member for the IEEE Solid-State Circuits Society and an IEEE CAS distinguished lecturer.