CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies

Process-Aware SRAM Design and Test
1. Auflage. Softcover version of original hardcover Auflage 2008
ISBN: 978-90-481-7855-1
Verlag: Springer Netherlands

Buch, Englisch, Band 40, 194 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 330 g

Reihe: Frontiers in Electronic Testing

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.

Zielgruppe

Research

Autoren/Hrsg.

Sachdev, Manoj

Pavlov, Andrei

Fachgebiete

• Mathematik | Informatik EDV | Informatik Technische Informatik Hochleistungsrechnen, Supercomputer
• Mathematik | Informatik EDV | Informatik Daten / Datenbanken Datenkompression, Dokumentaustauschformate
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

and Motivation.- SRAM Circuit Design and Operation.- SRAM Cell Stability: Definition, Modeling and Testing.- Traditional SRAM Fault Models and Test Practices.- Techniques for Detection of SRAM Cells with Stability Faults.- Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques.

Über Autor(innen)

Prof. Sachdev has authored several successful books with Springer