Buch, Englisch, 344 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 540 g
Reihe: IFIP Advances in Information and Communication Technology
VLSI-SoC: From Systems to Silicon
1. Auflage. Softcover version of original hardcover Auflage 2007
ISBN: 978-1-4419-4467-2
Verlag: Springer
IFIP TC10/ WG 10.5 Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2005), October 17-19, 2005, Perth, Australia
Buch, Englisch, 344 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 540 g
Reihe: IFIP Advances in Information and Communication Technology
ISBN: 978-1-4419-4467-2
Verlag: Springer
This book contains extended and revised versions of the best papers that were presented during the thirteenth edition of the IFIP TC 10 International Conference on Very Large Scale Integration, a Global System-on-Chip Design and CAD conference. This conference provides a forum to exchange ideas and show industrial and academic research results in the field of microelectronics design.
Zielgruppe
Research
Autoren/Hrsg.
Fachgebiete
Weitere Infos & Material
Molecular Electronics – Devices and Circuits Technology.- Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.- A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.- Defragmentation Algorithms for Partially Reconfigurable Hardware.- Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits.- 3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System.- Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms.- A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis.- Issues in Model Reduction of Power Grids.- A Traffic Injection Methodology with Support for System-Level Synchronization.- Pareto Points in SRAM Design Using the Sleepy Stack Approach.- Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.- Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping.- A Novel MicroPhotonic Structure for Optical Header Recognition.- Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint.- On-chip Pseudorandom Testing for Linear and Nonlinear MEMS.- Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.- On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction.- Exact BDD Minimization for Path-Related Objective Functions.- Current Mask Generation: an Analog Circuit to Thwart DPA Attacks.- A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming.
