Reis / Osseiran / Pfleiderer VLSI-SoC: From Systems to Silicon

IFIP TC10/ WG 10.5 Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2005), October 17-19, 2005, Perth, Australia
1. Auflage 2007
ISBN: 978-0-387-73661-7
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 240, 342 Seiten

Reihe: IFIP Advances in Information and Communication Technology

This book contains extended and revised versions of the best papers that were presented during the thirteenth edition of the IFIP TC 10 International Conference on Very Large Scale Integration, a Global System-on-Chip Design and CAD conference. The purpose of this conference is to provide a forum to exchange ideas and show industrial and academic research results in the field of microelectronics design. The current trend toward increasing chip integration and technology process advancements brings about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems.

Autoren/Hrsg.

Reis, Ricardo

Osseiran, Adam

Pfleiderer, Hans-Joerg

Inhaltsverzeichnis

1;CONTENTS;6
2;PREFACE;9
3;Molecular Electronics - Devices and Circuits Technology;11
4;Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals;21
5;A Comparison of Layout Implementationsof Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures;35
6;Defragmentation Algorithms for Partially Reconfigurable Hardware;50
7;Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits;63
8;3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System;78
9;Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms;94
10;A Methodology for Reliability Enhancement of Nanometer- Scale Digital Systems Based on a- priori Functional Fault- Tolerance Analysis;117
11;Issues in Model Reduction of Power Grids;132
12;A Traffic Injection Methodology with Support for System- Level Synchronization;150
13;Pareto Points in SRAM Design Using the Sleepy Stack Approach;167
14;Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs;182
15;Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping;198
16;A Novel MicroPhotonic Structure for Optical Header Recognition ;211
17;Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint;222
18;On-chip Pseudorandom Testing for Linear and Nonlinear MEMS;246
19;Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles;268
20;On The Design of A Dynamically Reconfigurable Function- Unit for Error Detection and Correction;283
21;Exact BDD Minimization for Path-Related Objective Functions;298
22;Current Mask Generation: an Analog Circuit to Thwart DPA Attacks;315
23;A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming;329