Radetzki Languages for Embedded Systems and their Applications

Selected Contributions on Specification, Design, and Verification from FDL'08
1. Auflage 2009
ISBN: 978-1-4020-9714-0
Verlag: Springer Netherlands
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 36, 324 Seiten

Reihe: Lecture Notes in Electrical Engineering

Embedded systems take over complex control and data processing tasks in diverse application ?elds such as automotive, avionics, consumer products, and telec- munications. They are the primary driver for improving overall system safety, ef?ciency, and comfort. The demand for further improvement in these aspects can only be satis?ed by designing embedded systems of increasing complexity, which in turn necessitates the development of new system design methodologies based on speci?cation, design, and veri?cation languages. The objective of the book at hand is to provide researchers and designers with an overview of current research trends, results, and application experiences in c- puter languages for embedded systems. The book builds upon the most relevant contributions to the 2008 conference Forum on Design Languages (FDL), the p- mier international conference specializing in this ?eld. These contributions have been selected based on the results of reviews provided by leading experts from - search and industry. In many cases, the authors have improved their original work by adding breadth, depth, or explanation.

Autoren/Hrsg.

Radetzki, Martin

Inhaltsverzeichnis

1;Preface;6
2;Contents;8
3;Model-Based System Specification Languages;16
3.1;Power and Energy Estimations in Model-Based Design;17
3.1.1;Introduction;17
3.1.2;AADL Component Based Design Flow;19
3.1.3;Consumption Analysis: the Methodology;21
3.1.4;Power Estimation;22
3.1.4.1;Power Models;23
3.1.4.2;Multi-level Estimation;25
3.1.4.2.1;Refinement Level 1;25
3.1.4.2.2;Refinement Level 2;26
3.1.4.2.3;Refinement Level 3;28
3.1.5;Power Estimation for Complex DSP;28
3.1.6;Power Estimation for Field Programmable Gate Array;30
3.1.7;Power Estimation for Operating System Services;31
3.1.7.1;Ethernet Communications Consumption Modelling;32
3.1.7.1.1;Analysis of Relevant Parameters;32
3.1.7.1.2;Power and Energy Characterisation;32
3.1.7.2;Models;33
3.1.8;Consumption Analysis Tool;34
3.1.8.1;Property Sets;34
3.1.9;Conclusion;37
3.1.10;References;38
3.2;MARTE vs. AADL for Discrete-Event and Discrete-Time Domains;41
3.2.1;Introduction;41
3.2.2;Marte Time Model;42
3.2.2.1;Definitions;43
3.2.2.2;Event-Triggered Communications;43
3.2.2.3;Time-Triggered Communications;44
3.2.2.4;Periodic Tasks and Physical Time;45
3.2.2.5;TimeSquare;45
3.2.3;AADL;45
3.2.3.1;Modeling Elements;45
3.2.3.2;AADL Application Software Components;46
3.2.3.3;AADL Flows;47
3.2.3.4;AADL Ports;47
3.2.4;Three Different Configurations;48
3.2.4.1;The Aperiodic Case;48
3.2.4.2;The Mixed Event-Data Flow Case;51
3.2.4.3;The Periodic Case;52
3.2.5;Conclusion;53
3.2.6;Glossary;54
3.2.7;References;54
3.3;Generation of MARTE Allocation Models from Activity Threads;56
3.3.1;Introduction;56
3.3.2;Related Work;58
3.3.3;Building System Models with MARTE;59
3.3.4;Utilizing Activity Threads for Design-Space Exploration;60
3.3.5;Generating MARTE Allocation Models with Activity Threads;61
3.3.6;A Prototypic Implementation of the Method;64
3.3.7;Visualization of Performance Feedback;66
3.3.8;Summary and Outlook;67
3.3.9;References;68
3.4;Model-Driven System Validation by Scenarios;70
3.4.1;Introduction;70
3.4.2;ASMs and ASMETA;72
3.4.3;Scenario-Based Validation of ASM Models;73
3.4.3.1;The AValLa Language;73
3.4.4;The Model-Driven Validation Environment;74
3.4.4.1;From SystemC UML Models to ASM Models;75
3.4.4.2;Model Validator;77
3.4.5;The Simple Bus Case Study;77
3.4.6;Related Work;79
3.4.7;Conclusions and Future Work;81
3.4.8;References;81
3.5;An Advanced Simulink Verification Flow Using SystemC;83
3.5.1;Introduction;83
3.5.2;Related Work;84
3.5.3;Extended Verification Flow;85
3.5.3.1;Conventional Flow;85
3.5.3.1.1;Conventional Test Bench Concept;86
3.5.3.1.2;Extended Test Bench Concept;87
3.5.3.2;Extending the Verification Flow;88
3.5.4;Implementation;89
3.5.4.1;Synchronization;89
3.5.4.2;Data Type Conversion;92
3.5.5;Evaluation;92
3.5.5.1;Implementation;92
3.5.5.2;Extended Verification Flow;94
3.5.6;Conclusion;95
3.5.7;References;96
4;Languages for Heterogeneous System Design;97
4.1;VHDL-AMS Implementation of a Numerical Ballistic CNT Model;98
4.1.1;Introduction;98
4.1.2;Mobile Charge Density and Self-Consistent Voltage;99
4.1.3;Numerical Piece-Wise Approximation of the Charge Density;100
4.1.4;Performance of Numerical Approximations;102
4.1.5;VHDL-AMS Implementation;104
4.1.6;Conclusion;109
4.1.6.1;Acknowledgements;110
4.1.7;References;110
4.2;Wide-Band Sigma-Delta ADC Design in Superconducting Technology;112
4.2.1;Introduction;112
4.2.2;Sigma-Delta Second Order Architecture;113
4.2.2.1;Bandpass Sigma-Delta Modulator;113
4.2.2.2;The Josephson Junction;114
4.2.2.3;The RSFQ Balanced Comparator;116
4.2.2.4;Sigma Delta Modulator Operation with Josephson Junctions;116
4.2.2.5;System Modeling with VHDL-AMS;117
4.2.3;The Sigma-Delta ADC Design;118
4.2.3.1;Clock and Comparator Design;118
4.2.4;Simulation Results;120
4.2.5;Conclusion;122
4.2.6;References;123
4.3;Heterogeneous and Non-linear Modeling in SystemC-AMS;124
4.3.1;Introduction;124
4.3.1.1;SystemC-AMS Modeling Platform;125
4.3.1.2;Summary of Electrostatic Harvester Operation;127
4.3.1.2.1;Resonant Electromechanical Transducer;127
4.3.1.2.2;Conditioning Circuit Operation;128
4.3.2;SystemC-AMS Modeling of the Harvester;129
4.3.2.1;Resonator Modeling;129
4.3.2.2;Implementation of the Conditioning Circuit Model;130
4.3.2.2.1;Variable Capacitor;130
4.3.2.2.2;Diode Implementation;130
4.3.2.2.3;Initial Charge of the Capacitors;133
4.3.2.2.4;Conditioning Circuit/Flyback Switch Modeling;134
4.3.2.2.5;Modeling of the Diode D3;134
4.3.2.3;Model of the Whole System;134
4.3.3;Modeling Results;135
4.3.3.1;Description of the Modeling Experiment;135
4.3.3.2;Modeling Results Validation;137
4.3.4;Conclusion;138
4.3.5;References;138
5;Digital Systems Design Methodologies Based on C++;140
5.1;Application Workload and SystemC Platform Modeling for Performance Evaluation;141
5.1.1;Introduction;141
5.1.2;Performance Modeling and Simulation;143
5.1.2.1;Application and Workload Modeling;143
5.1.2.2;Execution Platform Modeling;144
5.1.2.2.1;Component Layer;145
5.1.2.2.2;Subsystem Layer;145
5.1.2.2.3;Platform Architecture Layer;145
5.1.2.2.4;Interfaces;146
5.1.2.3;Allocation and Transformation to SystemC;147
5.1.2.4;Performance Simulation;148
5.1.3;Mobile Video Player Case Example;148
5.1.3.1;Modeling of the Execution Platform Components;149
5.1.3.2;Modeling of the Services;151
5.1.3.3;Modeling of the Application;153
5.1.3.4;Analysis of Simulation Results;154
5.1.4;Conclusions;155
5.1.4.1;Acknowledgements;156
5.1.5;References;156
5.2;Adaptive Interconnect Models for Transaction-Level Simulation;158
5.2.1;Introduction;158
5.2.2;Related Work;160
5.2.3;Adaptive Interconnect Models;161
5.2.3.1;Point-to-Point Communication;161
5.2.3.2;Bus-Based Communication;163
5.2.4;Model Implementation;166
5.2.4.1;An Adaptive FSL Model;166
5.2.4.2;An Adaptive AHB Model;167
5.2.5;Experimental Results;169
5.2.6;Conclusion;173
5.2.7;References;173
5.3;Efficient Architecture Evaluation Using Functional Mapping;175
5.3.1;Introduction;175
5.3.1.1;Functional Mapping;176
5.3.1.2;Timing Behavior;177
5.3.2;Conventional Code Transformation;177
5.3.3;Optimization Approach;179
5.3.3.1;Class Unitized;179
5.3.4;Customize and Apply Unitized;181
5.3.4.1;Application of u_trace;182
5.3.5;Using the Approach in the Design Flow;183
5.3.5.1;Handling Arrays;183
5.3.5.2;Design Example;184
5.3.5.3;Simulation Results;186
5.3.6;Limitations and Experiences;187
5.3.7;Summary;189
5.3.7.1;Outlook;189
5.3.8;References;189
5.4;Symbolic Scheduling of SystemC Dataflow Designs;191
5.4.1;Introduction;191
5.4.2;Model of Computation;192
5.4.3;Symbolic Representation;195
5.4.4;QSS of SysteMoC Models;197
5.4.4.1;Transition Graphs;198
5.4.4.2;Path Searching;199
5.4.4.3;Scheduling Algorithm;201
5.4.5;Related Work;203
5.4.6;Example;204
5.4.7;Conclusions and Further Work;205
5.4.8;References;206
5.5;SystemC Simulation of Networked Embedded Systems;208
5.5.1;Introduction;208
5.5.2;The Architecture of SCNSL;210
5.5.2.1;Main Components of SCNSL;211
5.5.3;Main Problems Solved by SCNSL;214
5.5.3.1;Simulation of RTL Models;214
5.5.3.2;Assessment of Transmission Validity;214
5.5.3.3;Simulation Planning;215
5.5.3.4;Application to a Wireless Scenario;215
5.5.4;Experimental Results;217
5.5.5;Conclusions;217
5.5.6;References;218
5.6;Modeling of Embedded Software Multitasking in SystemC/OSSS;219
5.6.1;Introduction;219
5.6.2;Related Work;220
5.6.3;The OSSS Design Flow;222
5.6.3.1;Application Layer;222
5.6.3.2;Virtual Target Architecture Layer;223
5.6.4;Modeling Software in OSSS;224
5.6.4.1;Abstraction of Run-time System;224
5.6.4.2;Software Tasks;225
5.6.4.3;Software Shared Objects;226
5.6.4.4;Software Execution Times;227
5.6.5;Exploration of Platform Effects;228
5.6.6;Simulation Results;229
5.6.6.1;Accuracy and Performance;229
5.6.6.2;Lazy Synchronization;230
5.6.7;Conclusion;231
5.6.8;References;231
5.7;High-Level Reconfiguration Modeling in SystemC;233
5.7.1;Introduction;233
5.7.2;Related Work;234
5.7.3;Basic Reconfiguration Modeling;235
5.7.3.1;Interpreting Reconfiguration as Circuit Switch;235
5.7.3.2;Creating Reconfigurable Modules from Static Ones;236
5.7.3.3;Control;237
5.7.4;Advanced ReChannel Features;237
5.7.4.1;Exportals;237
5.7.4.2;Synchronization;238
5.7.5;Explicit Description of Reconfiguration;239
5.7.5.1;Resettable Processes;240
5.7.5.2;Resettable Components;242
5.7.5.3;Binding Groups of Switches;243
5.7.6;Case Study;244
5.7.7;Conclusion and Future Work;245
5.7.8;References;246
5.8;Stream Programming for FPGAs;247
5.8.1;Introduction;247
5.8.2;Stream Computing;249
5.8.2.1;Streaming on FPGAs;250
5.8.3;Compiling Brook to Hardware;250
5.8.3.1;Example Brook Program;252
5.8.3.2;Exploiting Data Parallelism;254
5.8.4;Experimental Evaluation;256
5.8.4.1;Results;257
5.8.5;Concluding Remarks;258
5.8.6;References;259
6;Verification and Requirements Evaluation;260
6.1;A New Verification Technique for Custom-Designed Components at the Arithmetic Bit Level;261
6.1.1;Introduction;261
6.1.2;Normalization Method;263
6.1.2.1;ABL Normalization;263
6.1.2.1.1;Merging of Addition Networks;265
6.1.2.1.2;Distribution of Partial Products;266
6.1.2.2;Mixed ABL/Gate-Level Problems;266
6.1.3;Synthesis of ABL Descriptions from Gate-Level Models;267
6.1.3.1;Generation of the Equivalent ABL Descriptions for Boolean Functions in Reed-Muller Form;268
6.1.4;Experimental Results;272
6.1.5;Conclusion and Future Work;275
6.1.6;References;276
6.2;Debugging Contradictory Constraints in Constraint-Based Random Simulation;277
6.2.1;Introduction;277
6.2.2;SystemC Verification Library;279
6.2.3;Contradiction Analysis;280
6.2.3.1;Problem Formulation;280
6.2.3.2;Concepts for Contradiction Analysis;281
6.2.4;Implementation;284
6.2.5;Experimental Evaluation;286
6.2.5.1;Types of Contradictions;287
6.2.5.2;Effect of Property 1 and Property 2;288
6.2.5.3;Real-Life Example;289
6.2.6;Conclusions;292
6.2.7;References;293
6.3;Design of Communication Infrastructures for Reconfigurable Systems;295
6.3.1;Introduction;295
6.3.2;Related Works;297
6.3.3;Real World Applications Analysis;297
6.3.3.1;Applications Layer;298
6.3.3.2;Scenarios Layer;299
6.3.3.3;Characteristics Layer;299
6.3.3.4;Metrics Layer;300
6.3.4;The Proposed Solution;301
6.3.4.1;High Level Description;302
6.3.4.2;High Level Network Simulation;303
6.3.4.3;Evaluation and Selection;305
6.3.4.4;Verification and Validation;306
6.3.5;Results;306
6.3.6;Concluding Remarks;310
6.3.7;References;310
6.4;Analysis of Non-functional Properties of MPSoC Designs;312
6.4.1;Introduction;312
6.4.2;Related Work;314
6.4.3;Preliminaries;315
6.4.3.1;Activity Model;315
6.4.3.2;Power Management Model;316
6.4.4;Design Flow;316
6.4.5;Abstraction of System Functionality;317
6.4.6;Simulation Model Generation;318
6.4.6.1;Communication Dependency Graphs;318
6.4.6.2;Temporal Environment Models;319
6.4.6.3;Integration of Power Consumption and Power Management;321
6.4.6.4;Battery Models, Placement and Chip Environment;322
6.4.7;Experimental Results;323
6.4.8;Conclusions;325
6.4.9;References;326