E-Book, Englisch, 522 Seiten, eBook
ISBN: 978-0-306-48139-0
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark
was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion of techniques and methodologies for improving the power efficiency of CMOS circuits (digital and analog), systems on chip, microelectronic systems, wirelessly networked systems of computational nodes and so on. In addition to providing an in-depth analysis of the sources of power dissipation in VLSI circuits and systems and the technology and design trends, this book provides a myriad of state-of-the-art approaches to power optimization and control.
The different chapters of
Power Aware Design Methodologies
have been written by leading researchers and experts in their respective areas. Contributions are from both academia and industry. The contributors have reported the various technologies, methodologies, and techniques in such a way that they are understandable and useful.
Zielgruppe
Research
Autoren/Hrsg.
Weitere Infos & Material
CMOS Device Technology Trends for Power-Constrained Applications.- Low Power Memory Design.- Low-Power Digital Circuit Design.- Low Voltage Analog Design.- Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chip.- Power Optimization by Datapath Width Adjustment.- Energy-Efficient Design of High-Speed Links.- System and Microarchitectural Level Power Modeling, Optimization, and Their Implications in Energy Aware Computing.- Tools and Techniques for Integrated Hardware-Software Energy Optimizations.- Power-Aware Communication Systems.- Power-Aware Wireless Microsensor Networks.- Circuit and System Level Power Management.- Tools and Methodologies for Power Sensitive Design.- Reconfigurable Processors — The Road to Flexible Power-Aware Computing.- Energy-Efficient System-Level Design.
