Logic Synthesis for Low Power VLSI Designs

1998
ISBN: 978-0-7923-8076-4
Verlag: Springer US

Buch, Englisch, 236 Seiten, Format (B × H): 160 mm x 241 mm, Gewicht: 1190 g

presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.

Zielgruppe

Research

Autoren/Hrsg.

Pedram, Massoud

Iman, Sasan

Fachgebiete

• Technische Wissenschaften Technik Allgemein Computeranwendungen in der Technik
• Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Geisteswissenschaften Design Produktdesign, Industriedesign
• Mathematik | Informatik EDV | Informatik Angewandte Informatik Computeranwendungen in Wissenschaft & Technologie

Inhaltsverzeichnis

I Background, Terminology, and Power Modeling.- 1 Introduction.- 2 Technology Independent Power Analysis and Modeling.- II Two-level Function Optimization for Low Power.- 3 Two-Level Logic Minimization in CMOS Circuits.- 4 Two-Level Logic Minimization in PLAs.- III Multi-level Network Optimization for Low Power.- 5 Logic Restructuring for Low Power.- 6 Logic Minimization for Low Power.- 7 Technology Dependent Optimization for Low Power.- 8 Post Mapping Structural Optimization for Low Power.- IV Power Optimization Methodology.- 9 POSE: Power Optimization and Synthesis Environment.- V Conclusion.- 10 Concluding Remarks.