Buch, Englisch, 470 Seiten, Format (B × H): 156 mm x 234 mm, Gewicht: 907 g
Reihe: Electronic Packaging
Buch, Englisch, 470 Seiten, Format (B × H): 156 mm x 234 mm, Gewicht: 907 g
Reihe: Electronic Packaging
ISBN: 978-0-8493-9622-9
Verlag: Taylor & Francis
The rapid growth of the electronic products market has created an increasing need for affordable, reliable, high-speed and high-density multi-layer printed circuit boards (PCBs). This book presents the technologies, algorithms, and methodologies for engineers and others developing the next generation of electronic products.
A vision of the future in advanced electronics
Advanced Routing of Electronic Modules provides both fundamental theory and advanced technologies for improving routing. Beginning chapters discuss approaches to approximate a minimum rectilinear Steiner tree from a minimum spanning tree and introduce ways to avoid obstacles for routing simple multi-terminal nets sequentially in a workspace. Timing delay, clock skew, and noise control requirements in signal integrity are described as well as computer-aided approaches to managing these requirements in high-speed PCB/MCM routing.
Later chapters present the two-layer wiring problem, rip-up and reroute approaches, and parallel routing, including global routing, boundary crossing placement, and detailed maze routing in hardware acceleration. Data structures, data management, and algorithms for parallel routing in a multiple-processor hardware systems are also covered.
Zielgruppe
Academic and Postgraduate
Autoren/Hrsg.
Weitere Infos & Material
(Section Headings): The General Solution of the Rectilinear Steiner's Problem and its Applications. Refinement Approaches for Rectilinear Steiner Tree Construction. Rectilinear Interconnections in Presence of Obstacles. Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs. Routing for Analog and Mixed Circuit. Segmented Channel Routing. Restricted Routing for CMOS Gate Arrays. Recent Developments in Wiring and Via Minimization. Layout Compactions for High-performance/Large-scale Circuits. Rip-up and Reroute Strategies. Parallel Routing. Appendix A: Symbols. Appendix B: Acronyms. Appendix C: Glossary. Index.
