Correct Hardware Design and Verification Methods

13th IFIP WG 10.5Advanced Research, Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings
2005
ISBN: 978-3-540-29105-3
Verlag: Springer Berlin Heidelberg

Buch, Englisch, 414 Seiten, Format (B × H): 155 mm x 235 mm, Gewicht: 1330 g

Reihe: Theoretical Computer Science and General Issues

viewpoint: we received a total number of 79 submitted papers, out of which 21 long contributionsand 18 short contributionswere accepted for presentationat the conf- enceandinclusioninthisvolume.Allpapersreceivedaminimumofthreereviews. For the conferenceprogram outside the refereed talks we put emphasis on the - latedtopicsoftoolintegrationandpervasivesystemveri?cation.Thedayprecedingthe workingconferencefeaturedhands-ondemonstrationsfornumerousveri?cationtools; italsofeaturedatutorialonsystemveri?cationbymembersoftheVerisoftproject.The overall program of CHARME 2005 included an invited keynote address by Wolfram B¨ uttner on industrial processor veri?cation and a round table discussion about mixed techniquesforverylargehardware-softwaresystemsinitiatedwithaninvitedpresen- tionbyMasaharuImaiandAkiraKitajima. A quality conference such as CHARME results from the work of many people. We wish to thank the membersof the ProgramCommittee and the externalreviewers fortheirhardworkinevaluatingthesubmissionsandinselectinghighqualitypapers.

Zielgruppe

Research

Autoren/Hrsg.

Paul, Wolfgang

Borrione, Dominique

Fachgebiete

• Mathematik | Informatik EDV | Informatik Programmierung | Softwareentwicklung Software Engineering Objektorientierte Softwareentwicklung
• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
• Technische Wissenschaften Technik Allgemein Computeranwendungen in der Technik
• Geisteswissenschaften Design Produktdesign, Industriedesign
• Mathematik | Informatik Mathematik Mathematik Interdisziplinär Systemtheorie
• Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
• Mathematik | Informatik EDV | Informatik Angewandte Informatik Computeranwendungen in Wissenschaft & Technologie
• Interdisziplinäres Wissenschaften Wissenschaften: Forschung und Information Kybernetik, Systemtheorie, Komplexe Systeme
• Mathematik | Informatik EDV | Informatik Informatik Logik, formale Sprachen, Automaten
• Mathematik | Informatik EDV | Informatik Technische Informatik Hardware: Grundlagen und Allgemeines
• Mathematik | Informatik EDV | Informatik Informatik Künstliche Intelligenz Wissensbasierte Systeme, Expertensysteme
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Robotik
• Mathematik | Informatik EDV | Informatik Programmierung | Softwareentwicklung Programmierung: Methoden und Allgemeines

Inhaltsverzeichnis

Invited Talks.- Is Formal Verification Bound to Remain a Junior Partner of Simulation?.- Verification Challenges in Configurable Processor Design with ASIP Meister.- Tutorial.- Towards the Pervasive Verification of Automotive Systems.- Functional Approaches to Design Description.- Wired: Wire-Aware Circuit Design.- Formalization of the DE2 Language.- Game Solving Approaches.- Finding and Fixing Faults.- Verifying Quantitative Properties Using Bound Functions.- Abstraction.- How Thorough Is Thorough Enough?.- Interleaved Invariant Checking with Dynamic Abstraction.- Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units.- Algorithms and Techniques for Speeding (DD-Based) Verification 1.- Efficient Symbolic Simulation via Dynamic Scheduling, Don’t Caring, and Case Splitting.- Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation.- Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning.- Real Time and LTL Model Checking.- Real-Time Model Checking Is Really Simple.- Temporal Modalities for Concisely Capturing Timing Diagrams.- Regular Vacuity.- Algorithms and Techniques for Speeding Verification 2.- Automatic Generation of Hints for Symbolic Traversal.- Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies.- A New SAT-Based Algorithm for Symbolic Trajectory Evaluation.- Evaluation of SAT-Based Tools.- An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment.- Model Reduction.- Exploiting Constraints in Transformation-Based Verification.- Identification and Counter Abstraction for Full Virtual Symmetry.- Verification of Memory Hierarchy Mechanisms.- On the Verificationof Memory Management Mechanisms.- Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification.- Short Papers.- Symbolic Partial Order Reduction for Rule Based Transition Systems.- Verifying Timing Behavior by Abstract Interpretation of Executable Code.- Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths.- Deadlock Prevention in the Æthereal Protocol.- Acceleration of SAT-Based Iterative Property Checking.- Error Detection Using BMC in a Parallel Environment.- Formal Verification of Synchronizers.- A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems.- Improvements to the Implementation of Interpolant-Based Model Checking.- High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design.- Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic.- Resolving Quartz Overloading.- FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers.- Predictive Reachability Using a Sample-Based Approach.- Minimizing Counterexample of ACTL Property.- Data Refinement for Synchronous System Specification and Construction.- Introducing Abstractions via Rewriting.- A Case Study: Formal Verification of Processor Critical Properties.