Pasricha / Dutt On-Chip Communication Architectures

System on Chip Interconnect
1. Auflage 2010
ISBN: 978-0-08-055828-8
Verlag: Elsevier Science & Techn.
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 544 Seiten, Web PDF

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.
This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.
KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

Autoren/Hrsg.

Pasricha, Sudeep

Dutt, Nikil

Inhaltsverzeichnis

1;Front Cover;1
2;On-Chip Communication Architectures: System on Chip Interconnect;4
3;Copyright Page;5
4;Contents;6
5;Preface;10
6;About the Authors;14
7;Acknowledgments;16
8;List of Contributors;18
9;CHAPTER 1 Introduction;20
9.1;1.1. Trends in System-On-Chip Design;20
9.2;1.2. Coping with Soc Design Complexity;22
9.3;1.3. ESL Design Flow;23
9.4;1.4. On-Chip Communication Architectures: A Quick Look;25
9.5;1.5. Book Outline;31
10;CHAPTER 2 Basic Concepts of Bus-Based Communication Architectures;36
10.1;2.1. Terminology;37
10.2;2.2. Characteristics of Bus-Based Communication Architectures;38
10.3;2.3. Data Transfer Modes;47
10.4;2.4. Bus Topology Types;52
10.5;2.5. Physical Implementation of Bus Wires;56
10.6;2.6. Discussion: Buses in the DSM Era;57
10.7;2.7. Summary;58
11;CHAPTER 3 On-Chip Communication Architecture Standards;62
11.1;3.1. Standard On-Chip Bus-Based Communication Architectures;63
11.2;3.2. Socket-Based On-Chip Bus Interface Standards;107
11.3;3.3. Discussion: Off-Chip Bus Architecture Standards;115
11.4;3.4. Summary;116
12;CHAPTER 4 Models for Performance Exploration;120
12.1;4.1. Static Performance Estimation Models;121
12.2;4.2. Dynamic (Simulation-Based) Performance Estimation Models;130
12.3;4.3. Hybrid Communication Architecture Performance Estimation Approaches;151
12.4;4.4. Summary;157
13;CHAPTER 5 Models for Power and Thermal Estimation;162
13.1;5.1. Bus Wire Power Models;164
13.2;5.2. Comprehensive Bus Architecture Power Models;172
13.3;5.3. Bus Wire Thermal Models;186
13.4;5.4. Discussion: PVT Variation-Aware Power Estimation;193
13.5;5.5. Summary;198
14;CHAPTER 6 Synthesis of On-Chip Communication Architectures;204
14.1;6.1. Bus Topology Synthesis;206
14.2;6.2. Bus Protocol Parameter Synthesis;215
14.3;6.3. Bus Topology and Protocol Parameter Synthesis;224
14.4;6.4. Physical Implementation Aware Synthesis;235
14.5;6.5. Memory–Communication Architecture Co-synthesis;249
14.6;6.6. Discussion: Physical and Circuit Level Design of On-Chip Communication Architectures;259
14.7;6.7. Summary;262
15;CHAPTER 7 Encoding Techniques for On-Chip Communication Architectures;272
15.1;7.1. Techniques for Power Reduction;274
15.2;7.2. Techniques for Reducing Capacitive Crosstalk Delay;297
15.3;7.3. Techniques for Reducing Power and Capacitive Crosstalk Effects;301
15.4;7.4. Techniques for Reducing Inductive Crosstalk Effects;303
15.5;7.5. Techniques for Fault Tolerance and Reliability;306
15.6;7.6. Summary;311
16;CHAPTER 8 Custom Bus-Based On-Chip Communication Architecture Design;320
16.1;8.1. Split Bus Architectures;320
16.2;8.2. Serial Bus Architectures;328
16.3;8.3. CDMA-Based Bus Architectures;329
16.4;8.4. Asynchronous Bus Architectures;332
16.5;8.5. Dynamically Reconfigurable Bus Architectures;337
16.6;8.6. Summary;355
17;CHAPTER 9 On-Chip Communication Architecture Refinement and Interface Synthesis;360
17.1;9.1. On-Chip Communication Architecture Refinement;362
17.2;9.2. Interface Synthesis;365
17.3;9.3. Discussion: Interface Synthesis;380
17.4;9.4. Summary;380
18;CHAPTER 10 Verification and Security Issues in On-Chip Communication Architecture Design;386
18.1;10.1. Verification of On-Chip Communication Protocols;388
18.2;10.2. Compliance Verification for IP Block Integration;395
18.3;10.3. Basic Concepts of SoC Security;407
18.4;10.4. Security Support in Standard Bus Protocols;410
18.5;10.5. Communication Architecture Enhancements for Improving SoC Security;410
18.6;10.6. Summary;414
19;CHAPTER 11 Physical Design Trends for Interconnects;422
19.1;11.1. DSM Interconnect Design;424
19.2;11.2. Low Power, High Speed Circuit Design Techniques;427
19.3;11.3. Global Power Distribution Networks;436
19.4;11.4. Clock Distribution Networks;440
19.5;11.5. 3-D Interconnects;446
19.6;11.6. Summary and Concluding Remarks;448
20;CHAPTER 12 Networks-On-Chip;458
20.1;12.1. Network Topology;462
20.2;12.2. Switching Strategies;467
20.3;12.3. Routing Algorithms;470
20.4;12.4. Flow Control;473
20.5;12.5. Clocking Schemes;477
20.6;12.6. Quality of Service;478
20.7;12.7. NoC Architectures;478
20.8;12.8. NoC Status and Open Problems;483
20.9;12.9. Summary;485
21;CHAPTER 13 Emerging On-Chip Interconnect Technologies;492
21.1;13.1. Optical Interconnects;493
21.2;13.2. RF/Wireless Interconnects;502
21.3;13.3. CNT Interconnects;509
21.4;13.4. Summary;520
22;Index;528
22.1;A;528
22.2;B;529
22.3;C;530
22.4;D;531
22.5;E;532
22.6;F;533
22.7;G;533
22.8;H;533
22.9;I;534
22.10;J;534
22.11;K;534
22.12;L;534
22.13;M;535
22.14;N;535
22.15;O;536
22.16;P;536
22.17;Q;537
22.18;R;538
22.19;S;538
22.20;T;540
22.21;U;540
22.22;V;541
22.23;W;541
22.24;X;541
22.25;Z;541