ASIC Physical Design: A Practical Guide to ASIC Design Implementation

1. Auflage 2022
ISBN: 978-90-481-9646-3
Verlag: SPRINGER NATURE

Buch, Englisch, 350 Seiten, Book

ASIC Physical Design is for anyone who would like to learn VLSI physical design as practiced in the industry. It is an essential introduction for senior undergraduates, graduates or for anyone starting work in the field of VLSI physical design. It covers all aspects of physical design, with related topics such as logic synthesis (from a physical design viewpoint), IP integration and design for manufacturing. It treats the physical design of very large scale integrated circuits in deep-submicron processes in a gradual and systematic manner. There are separate chapters dedicated to all the different tasks associated with ASIC physical design. In each chapter, real world examples show how decisions need to be made depending on the type of chips as well as the primary goals of the design methodology. It discusses the current capabilities of the available commercial EDA tools wherever applicable.

Zielgruppe

Upper undergraduate

Autoren/Hrsg.

Oey, James

Buddharaju, Pradeep

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)

Inhaltsverzeichnis

Preface
1. Logic Synthesis. Synopsys Design constraints (SDC). Floorplan based synthesis
2. Floorplanning. Chip level. Block level
3. Power distribution. Power estimation. Block powergrid. Top level powergrid. EM/IR drop. Routability. Wirebond vs. flip chip. Technology Stack / Metal Layer usage. Spice simulations for local power usage. Decoupling caps.
4. Clock distribution. Chip level. Block level.
5. Automated Place and Route. Flow.
6. Signal Integrity. Max transition. Repeater distance. Spice analysis. Current technology data. Glitch analysis. Crosstalk incremental delay. EDA solutions.
7.Timing. SDC ( Synopsys design constraints). OCV (on-chip variation). Budgetting. Timing categories. Signoff corners. Clock uncertainty (jitter, skew, hold margin). Correlation between Place-and-Route tool and signoff timing tool. Synchronous clocks / clock crossings. Strategies for fixing hold/setup. Location based OCV/SSTA. Dynamic Timing Analysis. Timing with metal fill.
8. Layout verification. DRC (design rule check). LVS (layout vs schematic). ANT (antenna checks). LEC (logic equivalency checks).
9. Design for Manufacturing / Design for Yield. 65nm and 45nm DFM rules. redundant via. metal fill. wire spreading. litho-aware yield enhancement.
10. IP integration. Layout guidelines. Library views.
11. 65nm, 45nm, 32nm & beyond.
12. Libraries. high density vs high speed stdcells and memories.