Nigussie Variation Tolerant On-Chip Interconnects

1. Auflage 2011
ISBN: 978-1-4614-0131-5
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 177 Seiten

Reihe: Analog Circuits and Signal Processing

This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems.

Introduction.- Interconnect Design Techniques.- On-Chip Wire Modeling.- Design of Delay-Insensitive Current Sensing Interconnects.- Enhancing Completion Detection Performance.- Energy Efficient Semi-Serial Interconnect.- Comparison of the Designed Interconnects.- Circuit Techniques for PVT Variation Tolerance.

Autoren/Hrsg.

Nigussie, Ethiopia Enideg

Inhaltsverzeichnis

1;Variation Tolerant On-Chip Interconnects;4
2;Preface;6
3;Acknowledgements;8
4;Contents;10
5;Chapter 1 Introduction;14
6;Chapter 2 Interconnect Design Techniques;24
7;Chapter 3 On-Chip Wire Modeling;37
8;Chapter 4 Design of Delay-Insensitive Current Sensing Interconnects;47
9;Chapter 5 Enhancing Completion Detection Performance;82
10;Chapter 6 Energy Efficient Semi-Serial Interconnect;103
11;Chapter 7 Comparison of the Designed Interconnects;128
12;Chapter 8 Circuit Techniques for PVT Variation Tolerance;135
13;References;165
14;Index;174