Nicopoulos / Narayanan / Das Network-on-Chip Architectures

A Holistic Design Exploration
1. Auflage 2009
ISBN: 978-90-481-3031-3
Verlag: Springer Netherlands
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 45, 223 Seiten

Reihe: Lecture Notes in Electrical Engineering

[2]. The Cell Processor from Sony, Toshiba and IBM (STI) [3], and the Sun UltraSPARC T1 (formerly codenamed Niagara) [4] signal the growing popularity of such systems. Furthermore, Intel's very recently announced 80-core TeraFLOP chip [5] exemplifies the irreversible march toward many-core systems with tens or even hundreds of processing elements. 1.2 The Dawn of the Communication-Centric Revolution The multi-core thrust has ushered the gradual displacement of the computati- centric design model by a more communication-centric approach [6]. The large, sophisticated monolithic modules are giving way to several smaller, simpler p- cessing elements working in tandem. This trend has led to a surge in the popularity of multi-core systems, which typically manifest themselves in two distinct incarnations: heterogeneous Multi-Processor Systems-on-Chip (MPSoC) and homogeneous Chip Multi-Processors (CMP). The SoC philosophy revolves around the technique of Platform-Based Design (PBD) [7], which advocates the reuse of Intellectual Property (IP) cores in flexible design templates that can be customized accordingly to satisfy the demands of particular implementations. The appeal of such a modular approach lies in the substantially reduced Time-To- Market (TTM) incubation period, which is a direct outcome of lower circuit complexity and reduced design effort. The whole system can now be viewed as a diverse collection of pre-existing IP components integrated on a single die.

Autoren/Hrsg.

Nicopoulos, Chrysostomos

Narayanan, Vijaykrishnan

Das, Chita R.

Inhaltsverzeichnis

1;FM.pdf;1
2;1.pdf;21
2.1;Chapter 1;21
2.1.1;Introduction;21
2.1.1.1;1.1 The Diminishing Returns of Instruction-Level Parallelism;21
2.1.1.2;1.2 The Dawn of the Communication-Centric Revolution;22
2.1.1.3;1.3 The Global Wiring Challenge;22
2.1.1.4;1.4 The Network-on-Chip (NoC) Solution;24
2.1.1.5;1.5 Overview of Research;26
2.1.1.5.1;1.5.1 Legend for Figs. 1.4 and 1.5;27
3;2.pdf;33
3.1;Chapter 2;33
3.1.1;A Baseline NoC Architecture;33
4;3.pdf;37
4.1;Chapter 3;38
4.1.1;ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39];38
4.1.1.1;3.1 Importance of Buffer Size and Organization;38
4.1.1.2;3.2 Related Work in Buffer Design;41
4.1.1.3;3.3 The Proposed Dynamic Virtual Channel Regulator (ViChaR);43
4.1.1.3.1;3.3.1 Variable Number of Virtual Channels;46
4.1.1.3.2;3.3.2 ViChaR Component Analysis;49
4.1.1.4;3.4 Simulation Results;54
4.1.1.4.1;3.4.1 Simulation Platform;54
4.1.1.4.2;3.4.2 Analysis of Results;54
4.1.1.5;3.5 Chapter Summary;58
5;4.pdf;60
5.1;Chapter 4;60
5.1.1;RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Ne;60
5.1.1.1;4.1 Introduction and Motivation;60
5.1.1.2;4.2 Related Work in Partitioned Router Architectures;62
5.1.1.3;4.3 The Proposed Row–Column (RoCo) Decoupled Router;63
5.1.1.3.1;4.3.1 Row–Column Switch;63
5.1.1.3.2;4.3.2 Blocking Delay;67
5.1.1.3.3;4.3.3 Concurrency Control for High-Contention Environments;69
5.1.1.3.4;4.3.4 Flexible and Reusable On-Chip Communication;70
5.1.1.4;4.4 Fault-Tolerance Through Hardware Recycling;70
5.1.1.5;4.5 Performance Evaluation;75
5.1.1.5.1;4.5.1 Simulation Platform;75
5.1.1.5.2;4.5.2 Energy Model;76
5.1.1.5.3;4.5.3 A Performance, Energy, and Fault-Tolerance (PEF) Metric;76
5.1.1.5.4;4.5.4 Performance Results;77
5.1.1.6;4.6 Chapter Summary;81
6;5.pdf;84
6.1;Chapter 5;84
6.1.1;Exploring FaultoTolerant Network-on-Chip Architectures [37];84
6.1.1.1;5.1 Introduction and Motivation;84
6.1.1.2;5.2 Simulation Platform Preliminaries;86
6.1.1.3;5.3 Handling Link Soft Faults;87
6.1.1.3.1;5.3.1 Flit-Based HBH Retransmission Scheme;88
6.1.1.3.2;5.3.2 Deadlock Recovery;91
6.1.1.3.2.1;5.3.2.1 Proposed Deadlock Recovery Scheme;91
6.1.1.3.2.2;5.3.2.2 Probing for Deadlock Detection and Recovery;95
6.1.1.4;5.4 Handling Soft Errors in Intra-Router Logic;96
6.1.1.4.1;5.4.1 Virtual Channel Arbiter Errors;97
6.1.1.4.2;5.4.2 Routing Computation Unit Errors;99
6.1.1.4.3;5.4.3 Switch Allocator Errors;100
6.1.1.4.4;5.4.4 Crossbar Errors;102
6.1.1.4.5;5.4.5 Retransmission Buffer Errors;102
6.1.1.4.6;5.4.6 Handshaking Signal Errors;102
6.1.1.5;5.5 Handling Hard Faults;102
6.1.1.5.1;5.5.1 Proximity-Aware (PA) Fault-Tolerant Routing Algorithm;103
6.1.1.5.2;5.5.2 Extension of PA Routing for Hot-Spot Avoidance;105
6.1.1.5.3;5.5.3 Service-Oriented Networking (SON);107
6.1.1.5.4;5.5.4 SON – Direction Lookup Table (DLT) and Service Information Provider (SIP);108
6.1.1.6;5.6 Chapter Summary;110
7;6.pdf;112
7.1;Chapter 6;112
7.1.1;On the Effects of Process Variation in Network-on-Chip Architectures [45];112
7.1.1.1;6.1 Introduction and Motivation;112
7.1.1.2;6.2 Related Work in Process Variation (PV);113
7.1.1.3;6.3 The Impact of PV on NoC Architectures;114
7.1.1.3.1;6.3.1 Evaluation Platform;114
7.1.1.3.2;6.3.2 PV Effects on Router Components;117
7.1.1.3.2.1;6.3.2.1 Input Buffers;117
7.1.1.3.2.2;6.3.2.2 Virtual Channel Arbitration (VA) and Switch Allocation (SA);119
7.1.1.3.2.3;6.3.2.3 Crossbar (XBAR)/Links;124
7.1.1.4;6.4 The Proposed SturdiSwitch Architecture;124
7.1.1.4.1;6.4.1 IntelliBuffer: A Leakage-Aware Elastic Buffer Structure;125
7.1.1.4.2;6.4.2 VA Compaction Mechanism;127
7.1.1.4.3;6.4.3 SA Folding Mechanism;130
7.1.1.5;6.5 Chapter Summary;134
8;7.pdf;135
8.1;Chapter 7;136
8.1.1;The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15];136
8.1.1.1;7.1 Introduction and Motivation;136
8.1.1.2;7.2 Exploration of Existing On-Chip Bus Architectures;138
8.1.1.2.1;7.2.1 Traditional Bus Architectures;138
8.1.1.2.1.1;7.2.1.1 Bus Segmentation;139
8.1.1.2.1.2;7.2.1.2 Bus Arbitration;139
8.1.1.2.2;7.2.2 TDMA Buses and Hybrid Interconnects;140
8.1.1.2.3;7.2.3 Constraints of Traditional Buses;141
8.1.1.2.4;7.2.4 CDMA Interconnects;142
8.1.1.3;7.3 The Dynamic Time-Division Multiple-Access (dTDMA) Bus;144
8.1.1.3.1;7.3.1 Operation of the Dynamic Timeslot Allocation;145
8.1.1.3.2;7.3.2 Implementation of the dTDMA Bus;146
8.1.1.3.3;7.3.3 Comparison with a Traditional Bus Architecture;147
8.1.1.3.4;7.3.4 dTDMA Bus Performance;149
8.1.1.3.4.1;7.3.4.1 Throughput;149
8.1.1.3.4.2;7.3.4.2 Average Latency;150
8.1.1.3.4.3;7.3.4.3 Arbitration Policy;152
8.1.1.3.4.4;7.3.4.4 Power Consumption;154
8.1.1.4;7.4 Comparison with Networks-on-Chip;155
8.1.1.4.1;7.4.1 Experimental Setup;155
8.1.1.4.2;7.4.2 Results;156
8.1.1.5;7.5 Interconnect Hybridization;158
8.1.1.5.1;7.5.1 Affinity Grouping;159
8.1.1.5.2;7.5.2 Simulation Methodology;160
8.1.1.5.3;7.5.3 Hybridization Results;161
8.1.1.6;7.6 Chapter Summary;163
9;8.pdf;164
9.1;Chapter 8;164
9.1.1;Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43];164
9.1.1.1;8.1 Introduction and Motivation;166
9.1.1.2;8.2 Background;166
9.1.1.2.1;8.2.1 NUCA Architectures;167
9.1.1.2.2;8.2.2 Network-In-Memory (NetInMem);167
9.1.1.2.3;8.2.3 Three-Dimensional (3D) Design and Architectures;168
9.1.1.3;8.3 A 3D NetInMem Architecture;170
9.1.1.3.1;8.3.1 The dTDMA Bus as a Communication Pillar;172
9.1.1.3.2;8.3.2 CPU Placement;174
9.1.1.4;8.4 3D L2 Cache Management;179
9.1.1.4.1;8.4.1 Processors and L2 Cache Organization;179
9.1.1.4.2;8.4.2 Cache Management Policies;180
9.1.1.4.2.1;8.4.2.1 Search Policy;180
9.1.1.4.2.2;8.4.2.2 Placement and Replacement Policy;180
9.1.1.4.2.3;8.4.2.3 Cache Line Migration Policy;181
9.1.1.5;8.5 Experimental Evaluation;181
9.1.1.5.1;8.5.1 Methodology;181
9.1.1.5.2;8.5.2 Results;183
9.1.1.6;8.6 Chapter Summary;186
10;9.pdf;188
10.1;Chapter 9;188
10.1.1;A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44];188
10.1.1.1;9.1 Introduction and Motivation;190
10.1.1.2;9.2 Three-Dimensional Network-on-Chip Architectures;193
10.1.1.2.1;9.2.1 A 3D Symmetric NoC Architecture;193
10.1.1.2.2;9.2.2 The 3D NoC-Bus Hybrid Architecture;194
10.1.1.2.3;9.2.3 A True 3D NoC Router;196
10.1.1.2.4;9.2.4 A Partially-Connected 3D NoC Router Architecture;199
10.1.1.3;9.3 The Proposed 3D Dimensionally-Decomposed (DimDe) NoC Router Architecture;199
10.1.1.4;9.4 Performance Evaluation;207
10.1.1.4.1;9.4.1 Simulation Platform;207
10.1.1.4.2;9.4.2 Energy Model;208
10.1.1.4.3;9.4.3 Performance Results;208
10.1.1.5;9.5 Chapter Summary;213
11;10.pdf;215
11.1;Chapter 10;215
11.1.1;Digest of Additional NoC MACRO-Architectural Research;215
11.1.1.1;10.1 A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects [42];215
11.1.1.2;10.2 Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects [46];217
11.1.1.3;10.3 Exploring the Effects of Data Compression in NoC Architectures [47];219
12;11.pdf;222
12.1;Chapter 11;222
12.1.1;Conclusions and Future Work;222
13;BM.pdf;225
13.1;Anchor 1;225