Buch, Englisch, 302 Seiten, Format (B × H): 160 mm x 241 mm, Gewicht: 670 g
ISBN: 978-0-387-76473-3
Verlag: Springer US
This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.
Zielgruppe
Research
Autoren/Hrsg.
Fachgebiete
Weitere Infos & Material
High-Level Synthesis Fundamentals.- Power Modeling and Estimation at Transistor and Logic Gate Levels.- Architectural Power Modeling and Estimation.- Power Reduction Fundamentals.- Energy or Average Power Reduction.- Peak Power Reduction.- Transient Power Reduction.- Leakage Power Reduction.- Conclusions and Future Direction.
