Mishra / Bhunia / Tehranipoor Hardware IP Security and Trust

1. Auflage 2017
ISBN: 978-3-319-49025-0
Verlag: Springer Nature Switzerland
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 351 Seiten

This book provides an overview of current Intellectual Property (IP) based System-on-Chip (SoC) design methodology and highlights how security of IP can be compromised at various stages in the overall SoC design-fabrication-deployment cycle. Readers will gain a comprehensive understanding of the security vulnerabilities of different types of IPs. This book would enable readers to overcome these vulnerabilities through an efficient combination of proactive countermeasures and design-for-security solutions, as well as a wide variety of IP security and trust assessment and validation techniques. This book serves as a single-source of reference for system designers and practitioners for designing secure, reliable and trustworthy SoCs.


Prabhat Mishra is an Associate Professor in the Department of Computer and Information Science and Engineering (CISE) at the University of Florida (UF) where he leads the CISE Embedded Systems Lab. His research interests include design automation of embedded systems, energy-aware computing, reconfigurable architectures, hardware security and trust, system validation and verification, and post-silicon debug. He received his B.E. from Jadavpur University, Kolkata in 1994, M.Tech. from the Indian Institute of Technology, Kharagpur in 1996, and Ph.D. from the University of California, Irvine in 2004 -- all in Computer Science and Engineering. Prior to joining University of Florida, he spent several years in various companies including Intel, Motorola, Synopsys and Texas Instruments. He has published four books and more than 100 research articles in premier international journals and conferences. His research has been recognized by several awards including the NSF CAREER Award from the National Science Foundation, IBM Faculty Award, two best paper awards (VLSI Design 2011 and CODES+ISSS 2003), five best paper nominations (including DAC'09 and DATE'12), and 2004 EDAA Outstanding Dissertation Award from the European Design Automation Association. He has also received the 2007 International Educator of the Year Award from the UF College of Engineering for his international research and teaching contributions. Swarup Bhunia received his B.E. (Hons.) from Jadavpur University, Kolkata, India, and the M.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA, in 2005. Currently, Dr. Bhunia is a professor in the department of Electrical and Computer Engineering at University of Florida, Gainesville, FL, USA. Earlier, Dr. Bhunia has served as the T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He has over ten years of research and development experience with over 200 publications in peer-reviewed journals and premier conferences and four books (three edited) in the area of VLSI design, CAD and test techniques. His research interests include low power and robust design, hardware security and trust, adaptive nanocomputing and novel test methodologies. He has worked in the semiconductor industry on RTL synthesis, verification, and low power design for about three years. Dr. Bhunia received IBM Faculty Award (2013), National Science Foundation (NSF) career development award (2011), Semiconductor Research Corporation (SRC) technical excellence award (2005), best paper award in International Conference on VLSI Design (VLSI Design 2012), best paper award in International Conference on Computer Design (ICCD 2004), best paper award in Latin American Test Workshop (LATW 2003), and best paper nomination in Asia and South Pacific Design Automation Conference (ASP-DAC 2006) and in Hardware Oriented Test and Security (HOST 2010), nomination for John S. Diekhoff Award, Case Western Reserve University (2010) and SRC Inventor Recognition Award (2009). Mark M. Tehranipoor is currently the Intel Charles E. Young Professor in Cybersecurity at the Department of Electrical and Computer Engineering, the University of Florida. His current research projects include: hardware security and trust, electronics supply chain security, counterfeit IC detection and prevention, and reliable and testable VLSI design. Prof. Tehranipoor has published over 250 journal articles and refereed conference papers and has given more than 150 invited talks and keynote addresses since 2006. In addition, he has published six books and ten book chapters. His projects are sponsored by both the industry (Semiconductor Research Corporation (SRC), Texas Instruments, Freescale, Comcast, Honeywell, LSI, Mentor Graphics, Juniper, R3Logic, Cisco, Qualcomm, MediaTeck, etc.) and the Government (NSF, ARO, MDA, DOD, AFOSR, DOE, etc.). Prior to joining University of Florida, Dr. Tehranipoor served as the founding director of the Center for Hardware Assurance, Security, and Engineering (CHASE) and the Comcast Center of Excellence in Security Innovation (CSI) at the University of Connecticut. Prof. Tehranipoor is a Senior Member of the IEEE, Golden Core Member of IEEE Computer Society, and Member of ACM and ACM SIGDA. He is also a member of Connecticut Academy of Science and Engineering (CASE).

Autoren/Hrsg.

Mishra, Prabhat

Bhunia, Swarup

Tehranipoor, Mark

Inhaltsverzeichnis

1;Acknowledgements;5
2;Contents;7
3;Abbreviations (Acronyms);9
4;Part I Introduction;13
4.1;1 Security and Trust Vulnerabilities in Third-Party IPs;14
4.1.1;1.1 Introduction;14
4.1.2;1.2 Design and Validation of SoCs;16
4.1.3;1.3 Security and Trust Vulnerabilities in Third-Party IPs;17
4.1.4;1.4 Trustworthy SoC Design Using Untrusted IPs;20
4.1.5;1.5 Book Organization;23
4.1.6;References;24
5;Part II Trust Analysis;26
5.1;2 Security Rule Check;27
5.1.1;2.1 Introduction;27
5.1.2;2.2 Security Assets and Attack Models;29
5.1.2.1;2.2.1 Asset;29
5.1.2.2;2.2.2 Potential Access to Assets;31
5.1.2.3;2.2.3 Potential Adversary for Intentional Attacks;32
5.1.3;2.3 DSeRC: Design Security Rule Check;33
5.1.3.1;2.3.1 Vulnerabilities;35
5.1.3.1.1;2.3.1.1 Sources of Vulnerabilities;35
5.1.3.1.2;2.3.1.2 Vulnerabilities at Different Abstraction Levels;38
5.1.3.2;2.3.2 Metrics and Rules;39
5.1.3.3;2.3.3 Workflow of DSeRC Framework;42
5.1.4;2.4 Development of DSeRC Framework;43
5.1.4.1;2.4.1 Vulnerabilities, Metrics, and Rules;43
5.1.4.2;2.4.2 Tool Development;44
5.1.4.3;2.4.3 Development of Design Guidelines for Security;44
5.1.4.4;2.4.4 Development of Countermeasure Techniques;44
5.1.5;2.5 Conclusion;45
5.1.6;References;45
5.2;3 Digital Circuit Vulnerabilities to Hardware Trojans;47
5.2.1;3.1 Introduction;47
5.2.2;3.2 The Gate-Level Design Vulnerability Analysis Flow;48
5.2.3;3.3 The Layout-Level Design Vulnerability Analysis Flow;50
5.2.3.1;3.3.1 Cell and Routing Analyses;50
5.2.3.2;3.3.2 Net Analysis;52
5.2.4;3.4 Trojan Analyses;56
5.2.5;3.5 Conclusions;60
5.2.6;References;60
5.3;4 Code Coverage Analysis for IP Trust Verification;62
5.3.1;4.1 Introduction;62
5.3.2;4.2 SoC Design Flow;63
5.3.3;4.3 Hardware Trojan Structure;65
5.3.4;4.4 Related Work;65
5.3.5;4.5 A Case Study for IP Trust Verification;68
5.3.5.1;4.5.1 Formal Verification and Coverage Analysis;69
5.3.5.2;4.5.2 Techniques for Suspicious Signals Reduction;71
5.3.5.2.1;4.5.2.1 Phase 1: Test Bench Generation and Suspicious Signal Identification;71
5.3.5.2.2;4.5.2.2 Phase 2: Suspicious Signals Analysis;72
5.3.6;4.6 Simulation Results;74
5.3.6.1;4.6.1 Benchmark Setup;74
5.3.6.2;4.6.2 Impact of Test Bench on Coverage Analysis;75
5.3.6.3;4.6.3 Reducing the Suspicious Signals;76
5.3.6.4;4.6.4 Trojan Coverage Analysis;78
5.3.7;4.7 Conclusion;79
5.3.8;References;79
5.4;5 Analyzing Circuit Layout to Probing Attack;82
5.4.1;5.1 Introduction;82
5.4.2;5.2 Microprobing Attack Techniques;85
5.4.2.1;5.2.1 Essential Steps in a Probing Attack;85
5.4.2.2;5.2.2 Microprobing Through Milling;86
5.4.2.3;5.2.3 Back-Side Techniques;87
5.4.2.4;5.2.4 Other Related Techniques;88
5.4.3;5.3 Protection Against Probing Attacks;89
5.4.3.1;5.3.1 Active Shields;89
5.4.3.2;5.3.2 Techniques to Attack and Secure Active Shields;90
5.4.3.2.1;5.3.2.1 Routing Overhead;90
5.4.3.2.2;5.3.2.2 Stuck on Top Metal Layer;91
5.4.3.3;5.3.3 Other Antiprobing Designs;93
5.4.3.4;5.3.4 Summary on Antiprobing Protections;94
5.4.4;5.4 Layout-Based Evaluation Framework;94
5.4.4.1;5.4.1 Motivation;94
5.4.4.2;5.4.2 Assessment Rules;95
5.4.4.3;5.4.3 State-of-the-Art Active Shield Model;97
5.4.4.4;5.4.4 Impact of Milling Angle upon Effect of Bypass Attack;99
5.4.4.5;5.4.5 Algorithm to Find Exposed Area;100
5.4.4.6;5.4.6 Discussions on Applications of Exposed Area Algorithm;104
5.4.5;5.5 Conclusion;104
5.4.6;References;105
5.5;6 Testing of Side-Channel Leakage of Cryptographic Intellectual Properties: Metrics and Evaluations;108
5.5.1;6.1 Introduction;108
5.5.2;6.2 Preliminaries on Statistical Testing and Testing of Hypothesis;110
5.5.2.1;6.2.1 Sampling and Estimation;111
5.5.2.2;6.2.2 Some Statistical Distributions;112
5.5.2.3;6.2.3 Estimation and Test of Significance;112
5.5.2.4;6.2.4 Test of Significance: Statistical Hypothesis Testing;113
5.5.3;6.3 Formalizing SCA and the Success Rate of Side-Channel Adversary: Guessing Entropy;115
5.5.3.1;6.3.1 Success Rate of a Side-Channel Adversary;115
5.5.3.2;6.3.2 Guessing Entropy of an Adversary;117
5.5.4;6.4 Leakage Detection in SCA Traces: NICV and SNR;117
5.5.4.1;6.4.1 Normalized Inter-Class Variance;118
5.5.4.2;6.4.2 NICV and SNR;120
5.5.4.3;6.4.3 Related Work in Leakage Detection;121
5.5.4.4;6.4.4 Case Study: Application on AES;121
5.5.5;6.5 Test Vector Leakage Assessment Methodology;123
5.5.6;6.6 Equivalence of NICV and TVLA;125
5.5.7;6.7 TVLA on Higher Order Side-Channel Attacks;127
5.5.7.1;6.7.1 Estimation of Mean;128
5.5.7.2;6.7.2 Estimation of Variance;130
5.5.8;6.8 Case Study: Private Circuit;131
5.5.8.1;6.8.1 Experimental Analysis and Result;132
5.5.8.1.1;6.8.1.1 Optimized SIMON;132
5.5.8.1.2;6.8.1.2 2-Input LUT Based SIMON;134
5.5.8.1.3;6.8.1.3 Synchronized 2-Input LUT Based SIMON;135
5.5.9;6.9 Conclusion;138
5.5.10;References;138
6;Part III Effective Countermeasures;141
6.1;7 Hardware Hardening Approaches Using Camouflaging, Encryption, and Obfuscation;142
6.1.1;7.1 Introduction;142
6.1.2;7.2 Terminology;144
6.1.3;7.3 State of the Art;144
6.1.3.1;7.3.1 Camouflaging;144
6.1.3.2;7.3.2 Logic Encryption;146
6.1.3.2.1;7.3.2.1 Attacks Against Logic Encryption;147
6.1.3.2.2;7.3.2.2 Logic Encryption Algorithms;148
6.1.3.3;7.3.3 State Obfuscation;149
6.1.4;7.4 Dynamic State-Deflection-Based Obfuscation Method;150
6.1.4.1;7.4.1 Overview of DSD Obfuscation;150
6.1.4.2;7.4.2 Black Hole State Creation for Gate-level Obfuscation;152
6.1.4.3;7.4.3 Dynamic Transition in Black Hole Cluster;153
6.1.4.4;7.4.4 Experimental Results;153
6.1.4.4.1;7.4.4.1 Experimental Setup;153
6.1.4.4.2;7.4.4.2 Hardening Capability Against Circuit Switching Activity Analysis Attack;154
6.1.4.4.3;7.4.4.3 Number of Unique State Register Patterns in Obfuscation Mode;157
6.1.4.4.4;7.4.4.4 Area and Power Overhead;158
6.1.4.5;7.4.5 Discussion;159
6.1.5;7.5 Obfuscation for Three-Dimensional ICs;159
6.1.5.1;7.5.1 Leveraging 3D for Security;159
6.1.5.2;7.5.2 Trustworthiness of Vertical Communication;160
6.1.5.3;7.5.3 Proposed Obfuscation Method for 3D ICs;161
6.1.5.3.1;7.5.3.1 Overview of Proposed 3D Obfuscation Method;161
6.1.5.3.2;7.5.3.2 Proposed 3D Router Design;163
6.1.5.3.3;7.5.3.3 Assessment on 3D Obfuscation Method;165
6.1.5.4;7.5.4 Discussion;167
6.1.6;7.6 Summary;167
6.1.7;References;167
6.2;8 A Novel Mutating Runtime Architecture for Embedding Multiple Countermeasures Against Side-Channel Attacks;171
6.2.1;8.1 Introduction;171
6.2.2;8.2 Mutating Runtime Architecture;173
6.2.2.1;8.2.1 Design Properties;173
6.2.2.2;8.2.2 Online Allocation Method;174
6.2.2.3;8.2.3 DynamicBinding Method;176
6.2.2.4;8.2.4 FlexibleScheduling Method;178
6.2.3;8.3 Design Flow;180
6.2.4;8.4 Case Study: Block Cipher AES 128-Bit;181
6.2.4.1;8.4.1 Partitioning of the AES Modules;182
6.2.4.2;8.4.2 Implementation;183
6.2.4.2.1;8.4.2.1 Design Requirements;183
6.2.4.2.2;8.4.2.2 Data Path Architecture;184
6.2.4.2.3;8.4.2.3 Virtualization Scheme;186
6.2.4.2.4;8.4.2.4 Merging Round and Routines;186
6.2.4.3;8.4.3 Side-Channel Analysis Results;187
6.2.5;8.5 Summary;188
6.2.6;References;189
7;Part IV Security and Trust Validation;191
7.1;9 Validation of IP Security and Trust;192
7.1.1;9.1 Introduction;192
7.1.2;9.2 Logic Testing for Trojan Detection;193
7.1.2.1;9.2.1 Utilization Rarely Used Components for Trojan Detection;194
7.1.2.2;9.2.2 ATPG-Based Test Generation for Trojan Detection;195
7.1.3;9.3 Trojan Detection Using Equivalence Checking;196
7.1.3.1;9.3.1 Gröbner Basis Theory for Equivalence Checking of Arithmetic Circuits;197
7.1.3.2;9.3.2 Automated Debugging of Functional Trojans Using Remainders;201
7.1.3.2.1;9.3.2.1 Test Generation for Trojan Detection;203
7.1.3.2.2;9.3.2.2 Trojan Localization;204
7.1.4;9.4 Trojan Detection Using Model Checking;206
7.1.5;References;208
7.2;10 IP Trust Validation Using Proof-Carrying Hardware;211
7.2.1;10.1 Introduction;211
7.2.2;10.2 Overview of Formal Verification Methods for IP Protection;212
7.2.2.1;10.2.1 Threat Model;213
7.2.2.2;10.2.2 Formal Verification Methods;213
7.2.2.2.1;10.2.2.1 Theorem Prover;214
7.2.2.2.2;10.2.2.2 Model Checker;214
7.2.3;10.3 Proof-Carrying Hardware Framework for IP Protection;215
7.2.3.1;10.3.1 Semantic Translation;217
7.2.3.2;10.3.2 Data Protection Through Information Flow Tracking;219
7.2.3.2.1;10.3.2.1 Static Information Flow Tracking Scheme;220
7.2.3.2.2;10.3.2.2 Dynamic Information Assurance Scheme;221
7.2.3.3;10.3.3 Hierarchy Preserving Verification;222
7.2.3.4;10.3.4 Integrating Theorem Prover and Model Checker;224
7.2.4;10.4 Conclusion;226
7.2.5;References;226
7.3;11 Hardware Trust Verification;230
7.3.1;11.1 Introduction;230
7.3.2;11.2 HT Classification;231
7.3.2.1;11.2.1 Bug-Based HT;231
7.3.2.2;11.2.2 Parasite-Based HT;232
7.3.3;11.3 Verification Techniques for Hardware Trust;233
7.3.3.1;11.3.1 Functional Verification;233
7.3.3.2;11.3.2 Formal Verification;233
7.3.3.3;11.3.3 Trust Verification;233
7.3.3.3.1;11.3.3.1 Unused Circuit Identification;234
7.3.3.3.2;11.3.3.2 VeriTrust;235
7.3.3.3.3;11.3.3.3 FANCI;240
7.3.3.3.4;11.3.3.4 Discussion;242
7.3.4;11.4 Stealthy HT Designs Defeating Trust Verification;243
7.3.4.1;11.4.1 HTs Evade UCI;243
7.3.4.1.1;11.4.1.1 Motivational Case;243
7.3.4.2;11.4.2 HT Design Against UCI;244
7.3.4.3;11.4.3 HTs Evade VeriTrust;246
7.3.4.3.1;11.4.3.1 Motivational Case;246
7.3.4.3.2;11.4.3.2 HT Design Against VeriTrust;248
7.3.4.4;11.4.4 HTs Evade FANCI;250
7.3.4.4.1;11.4.4.1 Motivational Case;250
7.3.4.5;11.4.5 HT Design Against FANCI;252
7.3.4.6;11.4.6 Discussion;255
7.3.5;References;255
7.4;12 Verification and Trust for Unspecified IP Functionality;257
7.4.1;12.1 Introduction;257
7.4.1.1;12.1.1 Unspecified IP Functionality;257
7.4.1.2;12.1.2 Hardware Trojans;258
7.4.2;12.2 Trojans in RTL Don't Cares;261
7.4.2.1;12.2.1 Illustrative Examples;262
7.4.2.2;12.2.2 Automated Identification of Dangerous Don't Cares;265
7.4.2.3;12.2.3 Elliptic Curve Processor Case Study;267
7.4.2.3.1;12.2.3.1 The Hardware Trojan;267
7.4.2.3.2;12.2.3.2 Automated X-Analysis;268
7.4.3;12.3 Identifying Dangerous Unspecified Functionality;270
7.4.3.1;12.3.1 Background: Mutation Testing and Coverage Discounting;270
7.4.3.2;12.3.2 Identification Procedure;272
7.4.3.3;12.3.3 UART Communication Controller Case Study;274
7.4.3.3.1;12.3.3.1 The Wishbone Bus Trojan;275
7.4.3.3.2;12.3.3.2 Interrupt Output Signal Checker Bug;276
7.4.4;12.4 Trojans in Partially Specified On-chip Bus Functionality;277
7.4.4.1;12.4.1 Threat Model;278
7.4.4.2;12.4.2 Trojan Communication Channel;278
7.4.4.2.1;12.4.2.1 Topology Dependent Trojan Channel Properties;280
7.4.4.2.2;12.4.2.2 Protocol Dependent Trojan Channel Properties;280
7.4.4.3;12.4.3 AXI4-Lite Interconnect Trojan Example;281
7.4.4.3.1;12.4.3.1 Overhead;284
7.4.5;12.5 Conclusion;285
7.4.6;References;285
7.5;13 Verifying Security Properties in Modern SoCs Using Instruction-Level Abstractions;288
7.5.1;13.1 Introduction;288
7.5.1.1;13.1.1 Challenges in SoC Security Verification;289
7.5.1.1.1;13.1.1.1 Need for Hardware/Firmware Co-verification;290
7.5.1.1.2;13.1.1.2 SoC Verification Through Abstraction;290
7.5.1.1.3;13.1.1.3 Challenges in Specifying Security Properties;291
7.5.1.2;13.1.2 SoC Security Verification Using Instruction-Level Abstractions;292
7.5.1.2.1;13.1.2.1 ILA Synthesis and Verification;292
7.5.1.2.2;13.1.2.2 Security Verification Using the ILA;293
7.5.1.2.3;13.1.2.3 Summarizing ILA-Based Verification;293
7.5.2;13.2 Instruction-Level Abstractions;294
7.5.2.1;13.2.1 ILA Overview;294
7.5.2.2;13.2.2 ILA Definition;295
7.5.2.2.1;13.2.2.1 Notation;295
7.5.2.2.2;13.2.2.2 Architectural State and Inputs;295
7.5.2.2.3;13.2.2.3 Fetching an Instruction;296
7.5.2.2.4;13.2.2.4 Decoding an Instruction;296
7.5.2.2.5;13.2.2.5 Executing an Instruction;297
7.5.2.2.6;13.2.2.6 Syntax;297
7.5.2.2.7;13.2.2.7 Putting It All Together;298
7.5.2.3;13.2.3 ILA Synthesis;299
7.5.2.3.1;13.2.3.1 Notation and Problem Statement;299
7.5.2.3.2;13.2.3.2 Template Language;299
7.5.2.3.3;13.2.3.3 An Illustrative Example;300
7.5.2.3.4;13.2.3.4 Synthesis Algorithm;301
7.5.2.4;13.2.4 ILA Verification;302
7.5.2.4.1;13.2.4.1 Verifying Abstraction Correctness;303
7.5.2.4.2;13.2.4.2 Discussion of Verification Issues;303
7.5.2.4.3;13.2.4.3 Verification Correctness;304
7.5.2.5;13.2.5 Practical Case Study;304
7.5.2.5.1;13.2.5.1 Methodology;305
7.5.2.5.2;13.2.5.2 Example SoC Structure;305
7.5.2.5.3;13.2.5.3 Summary of Synthesis Results;305
7.5.2.5.4;13.2.5.4 Typical ILAs;306
7.5.2.5.5;13.2.5.5 Summary of Verification Results;307
7.5.3;13.3 Security Verification Using ILAs;309
7.5.3.1;13.3.1 System and Threat Model Overview;310
7.5.3.1.1;13.3.1.1 System-On-Chip Model;310
7.5.3.1.2;13.3.1.2 Threat Model;310
7.5.3.1.3;13.3.1.3 Security Objectives;310
7.5.3.1.4;13.3.1.4 Modelling the Attacker;311
7.5.3.2;13.3.2 Specifying Information Flow Properties;311
7.5.3.3;13.3.3 Firmware Execution Model;312
7.5.3.3.1;13.3.3.1 Execution State;312
7.5.3.3.2;13.3.3.2 A Review of Symbolic Execution;312
7.5.3.4;13.3.4 Verifying Information Flow Properties;315
7.5.3.5;13.3.5 Evaluation;318
7.5.3.5.1;13.3.5.1 Methodology;318
7.5.3.5.2;13.3.5.2 Security Objectives;318
7.5.3.5.3;13.3.5.3 Summary of Verification Results;319
7.5.4;13.4 Discussion and Related Work;319
7.5.4.1;13.4.1 SoC Security Verification;319
7.5.4.2;13.4.2 Related Work;320
7.5.4.2.1;13.4.2.1 Synthesizing Abstractions;320
7.5.4.2.2;13.4.2.2 SoC Verification;320
7.5.4.2.3;13.4.2.3 Symbolic Execution and Taint Analysis;321
7.5.5;13.5 Conclusion;321
7.5.6;References;321
7.6;14 Test Generation for Detection of Malicious Parametric Variations;325
7.6.1;14.1 Introduction;325
7.6.2;14.2 Power Virus for Gate-Level IPs;326
7.6.2.1;14.2.1 Pseudo-Boolean Satisfiability Approach;327
7.6.2.2;14.2.2 Largest Fanout First Approach;328
7.6.2.3;14.2.3 Cost-Benefit Analysis Approach;329
7.6.2.4;14.2.4 Power Virus for Sequential Circuits;330
7.6.3;14.3 Power Virus for Processor IPs;331
7.6.3.1;14.3.1 Stress Benchmarks;331
7.6.3.2;14.3.2 Power Virus Generation for Single-Core IPs;332
7.6.3.2.1;14.3.2.1 Exploration Space of Program Characteristics;333
7.6.3.2.2;14.3.2.2 Code Generation;334
7.6.3.3;14.3.3 Power Virus for Multi-Core IPs;335
7.6.3.3.1;14.3.3.1 Space Exploration of Program Characteristics;335
7.6.3.3.2;14.3.3.2 Multi-Threaded Power Virus Generation;336
7.6.4;14.4 Temperature Virus;336
7.6.4.1;14.4.1 Temperature Virus for Gate-Level IPs;336
7.6.4.2;14.4.2 Temperature Virus for Processor IPs;338
7.6.5;14.5 Conclusion;339
7.6.6;References;339
8;Part V Conclusion;341
8.1;15 The Future of Trustworthy SoC Design;342
8.1.1;15.1 Summary;342
8.1.1.1;15.1.1 Trust Vulnerability Analysis;342
8.1.1.2;15.1.2 Effective Countermeasures;343
8.1.1.3;15.1.3 Security and Trust Validation;343
8.1.2;15.2 Future Directions;344
8.1.2.1;15.2.1 Security and Trust Verification for Encrypted IPs;344
8.1.2.2;15.2.2 Security and Trust Verification for Obfuscated IPs;345
8.1.2.3;15.2.3 Security and Trust Verification for Hard IPs;345
8.1.2.4;15.2.4 Security and Trust Verification During SoC Design Flow;346
8.1.2.5;15.2.5 Unintentional Vulnerabilities;346
8.1.2.6;15.2.6 Multi-Security Objectives Design;347
8.1.2.7;15.2.7 Metrics and Benchmarks;347
8.1.3;References;348
9;Index;349