Micheloni / Marelli / Eshghi Inside Solid State Drives (SSDs)

1. Auflage 2012
ISBN: 978-94-007-5146-0
Verlag: Springer Netherlands
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 37, 382 Seiten

Reihe: Springer Series in Advanced Microelectronics

Solid State Drives (SSDs) are gaining momentum in enterprise and client applications, replacing Hard Disk Drives (HDDs) by offering higher performance and lower power. In the enterprise, developers of data center server and storage systems have seen CPU performance growing exponentially for the past two decades, while HDD performance has improved linearly for the same period. Additionally, multi-core CPU designs and virtualization have increased randomness of storage I/Os. These trends have shifted performance bottlenecks to enterprise storage systems. Business critical applications such as online transaction processing, financial data processing and database mining are increasingly limited by storage performance. In client applications, small mobile platforms are leaving little room for batteries while demanding long life out of them. Therefore, reducing both idle and active power consumption has become critical. Additionally, client storage systems are in need of significant performance improvement as well as supporting small robust form factors. Ultimately, client systems are optimizing for best performance/power ratio as well as performance/cost ratio. SSDs promise to address both enterprise and client storage requirements by drastically improving performance while at the same time reducing power.Inside Solid State Drives walks the reader through all the main topics related to SSDs: from NAND Flash to memory controller (hardware and software), from I/O interfaces (PCIe/SAS/SATA) to reliability, from error correction codes (BCH and LDPC) to encryption, from Flash signal processing to hybrid storage. We hope you enjoy this tour inside Solid State Drives.

Rino Micheloni ([e-mail]) is Lead Flash Technologist at IDT (Integrated Device Technology). He has 18 years experience in NAND/NOR Flash memory design, architecture and algorithms as well as the related intellectual property. Before IDT, he was Senior Principal for Flash and Director of Qimonda's design center in Italy, developing 36 nm and 48 nm NAND memories. From 2001 to 2006 he managed the Napoli design center of STMicroelectronics focusing on the development of 90 nm and 60 nm MLC NAND Flash. Before that, he led the development of MLC NOR Flash. He is co-author of 103 U.S. patents and five Springer books on NOR/NAND/ECC/SSD. He is IEEE Senior Member and received the STMicroelectronics Exceptional Patent in 2003 and 2004, and the Qimonda IP Award in 2007.  Alessia Marelli was born in Bergamo, Italy in 1980. She received her degree in Mathematical Science from 'Università degli Studi di Milano - Bicocca', Italy in 2003 with a thesis about ECC applied to Flash Memories. In 2003 she joined STMicroelectronics, Agrate B., Italy. She was involved in digital design of Multilevel NAND Memories, especially redundancy, ECC and algorithms. In 2007, she joined Qimonda as senior digital designer. In 2009 she joined Integrated Device Technology (IDT) as senior digital designer, where she takes care of ECC applied to SSD. She is co-author of some patents regarding Redundancy and ECC applied to Flash Memories. She is co-author of Memories in Wireless Systems (Springer, 2008), Error Correction Codes for Non-Volatile Memories (Springer, 2008), Inside NAND Flash Memories (Springer, 2010). Kam Eshghi is Sr. Director of Marketing in Enterprise Computing Division of IDT. Kam leads IDT's business strategy, marketing and business development for flash controllers and PCIe switches. Kam drove the creation of IDT's PCIe Enterprise Flash Controller product line and established IDT as a leader in this market.
Kam has more than 18 years of industry experience. Prior to joining IDT, Kam built product lines in server and networking markets at HP, Intel, Crosslayer Networks, and Synopsys.  During his time at Intel, Kam led a team to define strategy and product roadmaps for server chipsets.  Previous to that as Vice President of Marketing and Business Development at Crosslayer Networks, Kam defined a family of Ethernet-IP switch processors and led all customer engagements, ultimately leading to LSI's acquisition.
Kam holds a M.S. in Electrical Engineering & Computer Science from Massachusetts Institute of Technology, and a Master's in Business Administration and B.S. in Electrical Engineering & Computer Science both from University of California at Berkeley.

Autoren/Hrsg.

Micheloni, Rino

Marelli, Alessia

Eshghi, Kam

Inhaltsverzeichnis

1;Inside Solid State Drives(SSDs);3
1.1;Foreword;7
1.1.1;Error Correcting Coding for Solid State Disk Data Storage;7
1.2;Preface;9
1.3;About the Editors;13
1.4;Acknowledgements;15
1.5;Contents;17
1.6;Chapter 1: SSD Market Overview;19
1.6.1;1.1 Computing Market and Applications;19
1.6.2;1.2 SSD Overview;20
1.6.2.1;1.2.1 What Is a Solid State Drive?;20
1.6.2.2;1.2.2 The Memory Hierarchy;20
1.6.2.3;1.2.3 SSD vs. HDD;22
1.6.3;1.3 Client PC Applications;23
1.6.4;1.4 Notebook PCs and Tablets;25
1.6.5;1.5 Desktop PCs;26
1.6.6;1.6 Client PC and Tablet SSD Forecast;27
1.6.7;1.7 Enterprise Computing Applications;27
1.6.7.1;1.7.1 Transaction Processing;30
1.6.7.2;1.7.2 Video Server;31
1.6.7.3;1.7.3 High Performance Computing;31
1.6.7.4;1.7.4 Internet/Network Server;31
1.6.7.5;1.7.5 Server-Attached vs. Storage-Attached SSDs;32
1.6.8;1.8 Enterprise SSD Forecast;32
1.6.8.1;1.8.1 PCIe SSD;33
1.6.8.2;1.8.2 SATA Boot Drives;34
1.6.8.3;1.8.3 SATA Drives;34
1.6.8.4;1.8.4 Fiber Channel/SAS;34
1.6.9;References;35
1.7;Chapter 2: SSD Architecture and PCI Express Interface;36
1.7.1;2.1 Introduction;36
1.7.2;2.2 SSD Architecture;37
1.7.3;2.3 Non-volatile Memories;38
1.7.4;2.4 NAND Flash;39
1.7.4.1;2.4.1 NAND Array;39
1.7.4.2;2.4.2 NAND Interface;41
1.7.5;2.5 Memory Controller;43
1.7.5.1;2.5.1 Wear Leveling;45
1.7.5.2;2.5.2 Garbage Collection;46
1.7.5.3;2.5.3 Bad Block Management;47
1.7.5.4;2.5.4 Error Correction Code (ECC);47
1.7.6;2.6 Multi-channel Architecture;48
1.7.7;2.7 What Is PCIe?;50
1.7.8;2.8 The Need for Storage Speed;54
1.7.9;2.9 Why PCIe for SSD Interface?;55
1.7.10;2.10 PCIe SSD Implementations;57
1.7.11;2.11 Standards Driving Broader Adoption of PCIe SSDs;60
1.7.12;References;61
1.8;Chapter 3: SAS and SATA SSDs;63
1.8.1;3.1 Introduction;63
1.8.2;3.2 Enterprise vs. Consumer SSDs;64
1.8.3;3.3 SAS vs. SATA Protocol;67
1.8.3.1;3.3.1 Connectivity and High Availability;69
1.8.3.2;3.3.2 Form Factor and Capacity;71
1.8.3.3;3.3.3 Performance;72
1.8.4;3.4 What's Ahead;75
1.8.5;References;76
1.9;Chapter 4: Hybrid Storage;77
1.9.1;4.1 NAND Flash Memory and HDD;77
1.9.2;4.2 External NAND =+ HDD;79
1.9.3;4.3 NAND on Motherboard =+ HDD;81
1.9.4;4.4 NAND/SSD =+ HDD;82
1.9.5;4.5 Hybrid SSD;85
1.9.6;4.6 Over-Provisioning;87
1.9.7;References;90
1.10;Chapter 5: NAND Flash Technology;94
1.10.1;5.1 Flash for SSD Application;94
1.10.2;5.2 Introduction to Floating Gate NAND Operation;95
1.10.2.1;5.2.1 The Floating Gate NAND Memory Structure;96
1.10.2.2;5.2.2 The Floating Gate Cell Capacitive Coupling Model;97
1.10.2.3;5.2.3 Program and Erase of a Single Floating Gate Cell;99
1.10.2.4;5.2.4 Program, Erase, and Read of FG Cells in the NAND String;104
1.10.2.4.1;5.2.4.1 NAND Cell Programming and Self-Boosted Program Inhibit (SBPI);105
1.10.2.4.2;5.2.4.2 Erase and Read of FG Cells in the NAND String;108
1.10.3;5.3 Reliability of Floating Gate NAND Memory Cells;110
1.10.4;5.4 Scaling of Floating Gate NAND Memory Cells;113
1.10.4.1;5.4.1 Scaling of the Floating Gate Cell Geometry;114
1.10.4.2;5.4.2 Floating Gate Cell Cross-Coupling;116
1.10.4.3;5.4.3 Word Line to Word Line Leakage Current;119
1.10.4.4;5.4.4 Number of Stored Floating Gate Electrons;120
1.10.4.5;5.4.5 Random Telegraph Noise;122
1.10.5;5.5 Shrinking the Floating Gate NAND Technology Beyond the Direct Optical Lithography Limitation;124
1.10.6;5.6 Charge Trapping NAND Memory Cells as Floating Gate Cell Replacement;128
1.10.7;5.7 3D Memory Cell Integration for Future Mass Storage Applications;132
1.10.8;References;137
1.11;Chapter 6: NAND Flash Design;142
1.11.1;6.1 NAND Flash Memories;143
1.11.2;6.2 Logic Device View;143
1.11.2.1;6.2.1 Command Interface;144
1.11.2.2;6.2.2 Test Interface;145
1.11.2.3;6.2.3 Datapath;146
1.11.2.4;6.2.4 Microcontroller;148
1.11.3;6.3 NAND DDR Interface;149
1.11.3.1;6.3.1 DDR Interface;150
1.11.3.2;6.3.2 Power;152
1.11.3.3;6.3.3 Capacity;152
1.11.4;6.4 I/O Design;154
1.11.4.1;6.4.1 Basic CMOS Output Buffer Design;154
1.11.4.2;6.4.2 Simultaneous Switching Noise (SSN);155
1.11.4.3;6.4.3 High Speed NAND I/O Design;157
1.11.4.4;6.4.4 Double Data Rate OCD;157
1.11.4.4.1;6.4.4.1 OCD Linearity: Push-Pull and Open-Drain Configurations;158
1.11.4.4.2;6.4.4.2 Slew Rate Control and Bandwidth;158
1.11.4.4.3;6.4.4.3 Voltage Domain Change: Level Shifting;158
1.11.4.4.4;6.4.4.4 Jitter Sources and Duty Cycle Distortion;159
1.11.5;6.5 Read Operation: The Sense Amplifier;159
1.11.5.1;6.5.1 Interleaving Architecture;164
1.11.5.2;6.5.2 All BitLine (ABL) Architecture;166
1.11.5.3;6.5.3 Read Voltage with Thermal Tracking;170
1.11.6;6.6 Program;172
1.11.7;6.7 Erase;174
1.11.8;6.8 MLC and XLC Storage;175
1.11.9;6.9 High Voltage Management;177
1.11.9.1;6.9.1 Charge Pumps;177
1.11.9.2;6.9.2 Internal Supply Voltage Regulator;180
1.11.9.3;6.9.3 Double-Supply Voltage Regulator;181
1.11.10;6.10 Wordline Decoder;182
1.11.11;References;184
1.12;Chapter 7: NAND and Controller Co-design for SSDs;187
1.12.1;7.1 Introduction;187
1.12.2;7.2 Analysis of SSD Performance;189
1.12.3;7.3 Selective Bit-Line Precharge Scheme;193
1.12.4;7.4 Advanced Source-Line Program;195
1.12.5;7.5 Intelligent Interleaving;198
1.12.6;7.6 Sector Size Optimization;199
1.12.7;7.7 Adaptive Program-Voltage Generator for 3D-SSD;202
1.12.8;7.8 Asymmetric Coding;207
1.12.9;7.9 Stripe Pattern Elimination Algorithm;211
1.12.10;7.10 Conclusions;213
1.12.11;References;214
1.13;Chapter 8: SSD Reliability;216
1.13.1;8.1 Introduction;216
1.13.2;8.2 Reliability at Physical Level;217
1.13.2.1;8.2.1 NAND Flash Endurance;218
1.13.2.2;8.2.2 NAND Data Retention;220
1.13.2.3;8.2.3 Erratic Bits and Over-Programming;222
1.13.2.4;8.2.4 Reliability Considerations on SLC/MLC NAND Architectures;223
1.13.3;8.3 Reliability at Architectural Level;225
1.13.4;8.4 Reliability at System Level;227
1.13.4.1;8.4.1 RAID Systems;228
1.13.4.2;8.4.2 Caching;229
1.13.5;8.5 Reliable Data Management in Power Failure Scenarios;230
1.13.5.1;8.5.1 Power Failure Circuitry in SSDs;230
1.13.5.2;8.5.2 Supercapacitors;231
1.13.5.3;8.5.3 Discrete Capacitors;232
1.13.6;8.6 Endurance and Retention Verification in SSDs;233
1.13.6.1;8.6.1 SSD Endurance and Retention Rating;234
1.13.6.2;8.6.2 Endurance and Retention Stress Methods;235
1.13.6.3;8.6.3 Direct Method;236
1.13.6.3.1;8.6.3.1 Sample Size;236
1.13.6.3.2;8.6.3.2 Endurance Stress;237
1.13.6.3.3;8.6.3.3 Retention Stress;240
1.13.6.4;8.6.4 Extrapolation Method;241
1.13.6.4.1;8.6.4.1 Accelerated Write Rate Through Modified Workload;242
1.13.6.4.2;8.6.4.2 Extrapolation of FFR and Bad-Block Trends;242
1.13.6.4.3;8.6.4.3 FFR and UBER Estimation from Reduced-Capacity SSDs;243
1.13.7;8.7 Evaluating SSD Reliability Versus HDD Reliability;243
1.13.8;References;244
1.14;Chapter 9: Efficient Wear Leveling in NAND Flash Memory;245
1.14.1;9.1 Introduction;246
1.14.2;9.2 Evenness-Aware Algorithm;248
1.14.2.1;9.2.1 Algorithm Design;248
1.14.2.1.1;9.2.1.1 Overview;248
1.14.2.1.2;9.2.1.2 Block Erasing Table;249
1.14.2.1.3;9.2.1.3 SW Leveler;250
1.14.2.2;9.2.2 Worst-Case Analysis;252
1.14.2.2.1;9.2.2.1 Worst-Case Model for Extra Overheads;252
1.14.2.2.2;9.2.2.2 Extra Block Erases;253
1.14.2.2.3;9.2.2.3 Extra Live-Page Copyings;253
1.14.3;9.3 Dual-Pool Algorithm;254
1.14.3.1;9.3.1 Algorithm Design;254
1.14.3.1.1;9.3.1.1 Algorithm Concept;254
1.14.3.1.2;9.3.1.2 The Dual-Pool Algorithm: A Basic Form;256
1.14.3.1.3;9.3.1.3 Pool Adjustment;257
1.14.3.1.4;9.3.1.4 Algorithm Demonstration;259
1.14.3.2;9.3.2 Case Study: An SSD Implementation of the Dual-Pool Algorithm;261
1.14.3.2.1;9.3.2.1 The Firmware and Disk Emulation;261
1.14.3.2.2;9.3.2.2 Block-Wearing Information and Priority Queues;264
1.14.3.2.3;9.3.2.3 Segment Check-In/Check-Out;265
1.14.4;9.4 Conclusion;267
1.14.5;References;267
1.15;Chapter 10: BCH for Solid-State-Drives;270
1.15.1;10.1 Error Correction Codes Basic Definitions;270
1.15.2;10.2 BCH Codes;275
1.15.3;10.3 BCH Decoding Failures;281
1.15.4;10.4 Detection Properties;282
1.15.5;10.5 BCH Weight Estimation;283
1.15.6;10.6 BCH Weight Estimation: Real Cases Analysis;290
1.15.6.1;10.6.1 BCH[255,207,13];291
1.15.6.2;10.6.2 BCH[1023, 993,7];291
1.15.6.3;10.6.3 BCH[4095, 3975,21];293
1.15.6.4;10.6.4 BCH[16383, 15851,77];295
1.15.7;10.7 BCH Detection Conclusion;296
1.15.8;10.8 Multi-channel BCH;299
1.15.9;References;302
1.16;Chapter 11: Low-Density Parity-Check (LDPC) Codes;304
1.16.1;11.1 Shannon Limit;304
1.16.1.1;11.1.1 Entropy and Mutual Information;304
1.16.1.2;11.1.2 System Model and Channel Capacity;305
1.16.1.3;11.1.3 The Channel Coding Theorem;309
1.16.2;11.2 Maximum a Posteriori and Maximum Likelihood Decoding of Linear Block Codes;311
1.16.3;11.3 NAND Flash Memory Channel Model;311
1.16.3.1;11.3.1 SLC Channel Model;312
1.16.3.2;11.3.2 MLC Channel Model;314
1.16.4;11.4 Low-Density Parity-Check Codes;316
1.16.4.1;11.4.1 LDPC Code Ensembles;317
1.16.4.2;11.4.2 QC-LDPC Codes Construction;319
1.16.4.3;11.4.3 Error Floor;320
1.16.5;11.5 Belief Propagation (BP) Decoding of LDPC Codes;321
1.16.5.1;11.5.1 Introduction;321
1.16.5.2;11.5.2 Preliminaries;322
1.16.5.3;11.5.3 Algorithm Description;324
1.16.5.3.1;11.5.3.1 Overview;324
1.16.5.3.2;11.5.3.2 Initialization;326
1.16.5.3.3;11.5.3.3 Horizontal Step;327
1.16.5.3.4;11.5.3.4 Vertical Step;328
1.16.5.3.5;11.5.3.5 Hard Decision and Stopping Criterion;329
1.16.5.4;11.5.4 Log-Domain BP Decoder;330
1.16.6;11.6 Reduced-Complexity Decoders;333
1.16.6.1;11.6.1 Min-Sum Decoder;333
1.16.6.2;11.6.2 Gallager B Decoder;334
1.16.6.3;11.6.3 Flipping Algorithms;337
1.16.7;11.7 Numerical Example;338
1.16.8;References;340
1.17;Chapter 12: Protecting SSD Data Against Attacks;343
1.17.1;12.1 Challenges of SSD Security vs. HDD;343
1.17.2;12.2 Introduction to Cryptography;346
1.17.2.1;12.2.1 Basic Concepts;347
1.17.2.2;12.2.2 Cryptanalysis;352
1.17.2.3;12.2.3 Hash Functions;355
1.17.3;12.3 AES;359
1.17.3.1;12.3.1 Key Generator;360
1.17.3.2;12.3.2 AES Algorithm Core;360
1.17.4;12.4 SSD Security and Applications;363
1.17.5;References;364
1.18;Chapter 13: Flash Signal Processing and NAND/ReRAM SSD;366
1.18.1;13.1 Error Prediction (EP) LDPC [1];366
1.18.2;13.2 Error Recovery Scheme [1];371
1.18.3;13.3 3D TSV-Integrated Hybrid ReRAM/MLC NAND SSD [10];373
1.18.3.1;13.3.1 Data Management Algorithms [10];376
1.18.3.2;13.3.2 Performance, Power and Reliability [10];378
1.18.4;13.4 Conclusions;382
1.18.5;References;383
1.19;Index;384