Meneghini / Meneghesso / Zanoni Power GaN Devices

Materials, Applications and Reliability
1. Auflage 2017
ISBN: 978-3-319-43199-4
Verlag: Springer International Publishing
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 383 Seiten

Reihe: Power Electronics and Power Systems

This book presents the first comprehensive overview of the properties and fabrication methods of GaN-based power transistors, with contributions from the most active research groups in the field.  It describes how gallium nitride has emerged as an excellent material for the fabrication of power transistors; thanks to the high energy gap, high breakdown field, and saturation velocity of GaN, these devices can reach breakdown voltages beyond the kV range, and very high switching frequencies, thus being suitable for application in power conversion systems. Based on GaN, switching-mode power converters with efficiency in excess of 99 % have been already demonstrated, thus clearing the way for massive adoption of GaN transistors in the power conversion market. This is expected to have important advantages at both the environmental and economic level, since power conversion losses account for 10 % of global electricity consumption.The first part of the book describes the properties and advantages of gallium nitride compared to conventional semiconductor materials. The second part of the book describes the techniques used for device fabrication, and the methods for GaN-on-Silicon mass production. Specific attention is paid to the three most advanced device structures: lateral transistors, vertical power devices, and nanowire-based HEMTs. Other relevant topics covered by the book are the strategies for normally-off operation, and the problems related to device reliability. The last chapter reviews the switching characteristics of GaN HEMTs based on a systems level approach.
This book is a unique reference for people working in the materials, device and power electronics fields; it provides interdisciplinary information on material growth, device fabrication, reliability issues and circuit-level switching investigation.

Matteo Meneghini received the Ph.D. degree in the optimization of GaN-based LED and laser structures from the University of Padova, Italy. He is currently Assistant Professor at the Department of Information Engineering, University of Padova. During his career he has extensively worked on the reliability and parasitics of GaN-based semiconductor devices for application in the RF, power electronics and optoelectronics fields: his research is mainly focused towards the understanding of the physical mechanisms that limit the performance and the reliability of GaN-based LEDs, lasers, and HEMTs.
Gaudenzio Meneghesso received the Ph.D. degree in electrical and telecommunication engineering from the University of Padova, Padova, Italy, in 1997. In 1995, he was with the University of Twente, Enschede, The Netherlands, with a Human Capital and Mobility fellowship (within the SUSTAIN Network) working on the dynamic behavior of protection structures against electrostatic discharge (ESD). Since 2011, he has been a Full Professor with the Department of Information Engineering, University of Padova.
Enrico Zanoni was born in Verona, Italy, in 1956. He received the Laurea degree in physics (cum laude) from the University of Modena and Reggio Emilia, Modena, Italy, in 1982, after a student internship with the S. Carlo Foundation, Modena.  During 1985-1988, he was an Assistant Professor with the Faculty of Engineering, University of Bari, Bari, Italy. From 1988 to 1993, he frequently visited the U.S. and established research collaborations with Bell Laboratories; Hughes Research Laboratories; IBM T. J. Watson Research Center; Massachusetts Institute of Technology, Cambridge, MA, USA; TRW (currently, Northrop Grumman); University of California, Santa Barbara, CA, USA; and many other industrial and academic laboratories. During 1996-1997, he was a Full Professor of industrial electronics with the University of Modena and Reggio Emilia. He is currently with the University of Padova, Padua, Italy, where he was an Assistant Professor during 1988-1992, an Associate Professor of electronics during 1992-1993, a Full Professor of microelectronics during 1993-1996, and has been a Full Professor of digital electronics with the Department of Information Engineering since 1997.

Autoren/Hrsg.

Meneghini, Matteo

Meneghesso, Gaudenzio

Zanoni, Enrico

Inhaltsverzeichnis

1;Preface;6
2;Contents;9
3;1 Properties and Advantages of Gallium Nitride;11
3.1;1.1 General Background;11
3.2;1.2 GaN Material;12
3.3;1.3 Polarization Effect;16
3.4;1.4 GaN-Based FET;19
3.5;1.5 Natural Super Junction (NSJ) Structure;21
3.6;1.6 On-Resistance and Breakdown Voltage;24
3.7;1.7 Low-Voltage Devices;25
3.8;1.8 High-Voltage Devices;29
3.9;1.9 Future Study in GaN Vertical Power Device;33
3.10;References;35
4;2 Substrates and Materials;37
4.1;2.1 Substrate Overview;38
4.2;2.2 Metal-Organic Chemical Vapor Deposition;40
4.2.1;2.2.1 Fabrication of Semi-insulating (S.I.) (Al,Ga)N Layers;42
4.2.2;2.2.2 n- and p-Type Doping;43
4.2.3;2.2.3 AlGaN/GaN Heterostructures;44
4.3;2.3 Traps and Dispersion;45
4.4;2.4 Fabrication of Epitaxial Structures for Lateral Power Switching Devices;45
4.4.1;2.4.1 Current-Blocking Layer Deposition on Silicon Substrates;47
4.4.2;2.4.2 Current-Blocking Layer Deposition on Silicon Carbide Substrates;48
4.4.3;2.4.3 Current Blocking Layer Deposition on Sapphire Substrates;48
4.4.4;2.4.4 Gating Layer Growth;50
4.5;2.5 Vertical Devices;50
4.6;2.6 Outlook;55
4.6.1;2.6.1 InAlN and AlInGaN Barrier Layers;55
4.6.2;2.6.2 Devices Based on Non-c-plane GaN;56
4.7;References;57
5;3 GaN-on-Silicon CMOS-Compatible Process;63
5.1;3.1 GaN-on-Si Epitaxy;63
5.2;3.2 GaN-on-Si Au-Free Processing;65
5.3;3.3 Au-Free Ohmic Contact;69
5.3.1;3.3.1 AlGaN Barrier Recess;71
5.3.2;3.3.2 Ohmic Alloy Optimization;71
5.3.3;3.3.3 Ti/Al Ratio;72
5.3.4;3.3.4 Si Layer at Bottom of Ohmic Metal Stack;73
5.4;3.4 Gallium Contamination Issues;74
5.5;3.5 Conclusion;77
5.6;References;77
6;4 Lateral GaN Devices for Power Applications (from kHz to GHz);79
6.1;4.1 Introduction;79
6.2;4.2 History of AlGaN/GaN HEMTs;79
6.3;4.3 Addressing Dispersion;81
6.4;4.4 Gallium Nitride for mm-Wave Applications;84
6.5;4.5 Historical Perspective of N-Polar GaN Development;86
6.6;4.6 GaN Applied to Power Electronics;95
6.7;4.7 Conclusions;102
6.8;Acknowledgments;103
6.9;References;103
7;5 Vertical Gallium Nitride Technology;110
7.1;5.1 Introduction;110
7.2;5.2 Device Topology;112
7.2.1;5.2.1 Vertical Devices Versus Lateral Devices;112
7.3;5.3 Evolution of a CAVET;114
7.4;5.4 Design of a CAVET;117
7.4.1;5.4.1 A Discussion of the Key Components Required for the Successful Functioning of the Device;117
7.5;5.5 The Key Components of a CAVET;119
7.5.1;5.5.1 Current Blocking Layers;124
7.5.2;5.5.2 Performance and Cost;126
7.6;5.6 Role of Bulk GaN Substrate;127
7.7;5.7 CAVETs for RF Application;128
7.8;5.8 Conclusion;128
7.9;Acknowledgments;129
7.10;References;129
8;6 GaN-Based Nanowire Transistors;131
8.1;6.1 Introduction;131
8.1.1;6.1.1 Bottom-Up Nanowire Devices: GaN Nanowire Field-Effect Transistors;133
8.1.2;6.1.2 Top-Down Nanowire Devices;135
8.1.2.1;6.1.2.1 Tri-Gate GaN Transistors for Power Electronics Applications;135
8.2;6.2 Tri-Gate GaN Power MISFET;135
8.2.1;6.2.1 Additional Considerations of Tri-gate GaN Power Transistors;139
8.3;6.3 Nanowires for RF Applications: Increasing Linearity of Gm;142
8.4;6.4 Nanostructured GaN Schottky Barrier Diodes;145
8.4.1;6.4.1 Nanostructured Anode for GaN SBDs;145
8.5;6.5 Conclusions;148
8.6;References;150
9;7 Deep-Level Characterization: Electrical and Optical Methods;153
9.1;7.1 Introduction;153
9.2;7.2 Fundamentals of DLTS and DLOS;155
9.2.1;7.2.1 C-DLTS;155
9.2.2;7.2.2 C-DLOS;157
9.2.3;7.2.3 Applicability of C-DLTS and C-DLOS to HEMTs;158
9.2.4;7.2.4 I-DLTS and I-DLOS;159
9.3;7.3 Application of DLTS and DLOS to GaN HEMTs;161
9.3.1;7.3.1 Using Fill Pulses to Spatially Locate Traps;162
9.3.2;7.3.2 Using Measurement Bias to Spatially Locate Traps;166
9.3.3;7.3.3 Additional Methods to Measure Spatially Localized Traps;168
9.4;7.4 Conclusion;169
9.5;References;170
10;8 Modelling of GaN HEMTs: From Device-Level Simulation to Virtual Prototyping;172
10.1;8.1 Introduction;172
10.2;8.2 Device-Level Simulation;174
10.2.1;8.2.1 Pulsed Mode Behavior;177
10.3;8.3 Non-optimized Buffer Technology;177
10.4;8.4 Optimized Buffer Technology;181
10.4.1;8.4.1 AC Capacitances;183
10.4.2;8.4.2 Off-state Breakdown;185
10.5;8.5 Spice Model Development and Calibration;187
10.6;8.6 Application Board Characterization and Simulations;189
10.6.1;8.6.1 Normally-off pGaN Transistors;192
10.6.2;8.6.2 Normally-on HEMT: Cascode Design;195
10.7;8.7 Conclusions;201
10.8;References;201
11;9 Performance-Limiting Traps in GaN-Based HEMTs: From Native Defects to Common Impurities;204
11.1;9.1 Surface-Related Trapping;209
11.2;9.2 Impact of Iron Doping;212
11.2.1;9.2.1 Properties of Deep Level E2 and Impact of Iron Doping;212
11.2.2;9.2.2 Origin of the Trap E2;215
11.2.3;9.2.3 Impact of Electrical Stress on Trapping Mechanisms;217
11.3;9.3 Impact of Carbon Doping;219
11.4;9.4 Trapping Mechanisms in Metal Insulator Semiconductor High-Electron-Mobility Transistors (MIS-HEMTs);226
11.4.1;9.4.1 Origin of the Trapping Induced by Positive Gate Bias;227
11.4.2;9.4.2 Analysis of Fast and Slow Trapping Mechanisms;230
11.4.3;9.4.3 Materials and Deposition Techniques for the Improvement of Trapping Effects;230
11.5;References;234
12;10 Cascode Gallium Nitride HEMTs on Silicon: Structure, Performance, Manufacturing, and Reliability;244
12.1;10.1 Motivation and Configuration of the Cascode GaN HEMT;244
12.2;10.2 Functionality and Benefits of Cascode GaN HEMT;245
12.3;10.3 Key Applications and Performance Advantage of Cascode GaN HEMTs;246
12.3.1;10.3.1 Diode-Free Half-Bridge Architecture;246
12.3.2;10.3.2 Gate-Drive Considerations;247
12.4;10.4 Products in the Market;249
12.5;10.5 Applications and Key Performance Benefits;250
12.5.1;10.5.1Totem-Pole Power Factor Correction Circuit (PFC);250
12.5.2;10.5.2 PV Inverters;251
12.5.3;10.5.3 All-in-One Power Supplies with GaN AC–DC PFC and Full-Bridge Resonant Switching LLC DC–DC Con ...;251
12.6;10.6 Qualification and Reliability of Cascode GaN HEMTs;253
12.6.1;10.6.1 JEDEC Qualification;254
12.6.2;10.6.2 Extended Qualification/Reliability Testing;255
12.6.3;10.6.3 Operating and Intrinsic Lifetime Testing;256
12.7;10.7 Manufacturing Excellence;258
12.8;10.8 On Single-Chip e-Mode GaN;259
12.9;10.9 Future Outlook;260
12.9.1;10.9.1 Next-Generation Products;260
12.9.2;10.9.2 Intellectual Property Considerations;260
12.9.3;10.9.3 In Summary;260
12.10;Acknowledgments;261
12.11;References;261
13;11 Gate Injection Transistors: E-mode Operation and Conductivity Modulation;262
13.1;11.1Operation Principle of GIT;262
13.2;11.2DC and Switching Performances ofGIT;263
13.3;11.3 State-of-the-Art Reliability of GIT;268
13.4;11.4 Applications ofGIT to Practical Switching Systems;270
13.5;11.5 Advanced Technologies ofGIT for Future Power Electronics;275
13.6;11.6 Summary;278
13.7;Acknowledgments;278
13.8;References;279
14;12 Fluorine-Implanted Enhancement-Mode Transistors;280
14.1;12.1 Introduction: Fluorine in III-Nitride Heterostructures: Robust Vth Control;280
14.2;12.2 Physics Mechanism of Fluorine Implantation;282
14.2.1;12.2.1 Atomistic Modeling of F Plasma Ion Implantation;282
14.2.2;12.2.2 Stability of F Ions in AlGaN/GaN Heterostructures;284
14.2.3;12.2.3 Electron Binding Energy Around F Ions;287
14.3;12.3 Fluorine-Implanted Enhancement-Mode GaN MIS-HEMTs;288
14.3.1;12.3.1 GaN MIS-HEMTs;288
14.3.2;12.3.2 GaN MIS-HEMTs with Partially Recessed Fluorine-Implanted Barrier;291
14.3.3;12.3.3 GaN Smart Power ICs;293
14.4;12.4 Conclusions;298
14.5;Acknowledgments;298
14.6;References;299
15;13 Drift Effects in GaN High-Voltage Power Transistors;301
15.1;13.1 Introduction;301
15.2;13.2 Drift Effects and Their Physical Mechanisms;302
15.2.1;13.2.1 Overview;302
15.2.2;13.2.2 Basic Physical Understanding;302
15.2.3;13.2.3 Dependency on Device Operation Conditions;305
15.3;13.3 Drift Phenomena in GaN Power Switching Transistors;306
15.3.1;13.3.1 Dynamic On-State Resistance (Ron_dyn);306
15.3.1.1;13.3.1.1 Power Switching from Off-State Bias Point;307
15.3.1.2;13.3.1.2 Trapping Effects During On-State Operation;313
15.3.2;13.3.2Threshold Voltage Shift;313
15.3.3;13.3.3Kink Effect;314
15.4;13.4 Technological Countermeasures;316
15.4.1;13.4.1 Optimized Epitaxial Buffer Design;317
15.4.2;13.4.2 Reduction of Electrical Field in Critical Device Regions;318
15.5;Acknowledgments;320
15.6;References;320
16;14 Reliability Aspects of 650-V-Rated GaN Power Devices;324
16.1;14.1 Introduction;324
16.2;14.2Reliability of Au-Free Ohmic Contacts;324
16.2.1;14.2.1 Introduction to Ohmic Contact Reliability;324
16.2.2;14.2.2 Au-Free Ohmic Contacts Processing;325
16.2.3;14.2.3 Stressing and Measurement Procedure;326
16.2.4;14.2.4Reliability Evaluation of Au-Free Ohmic Contacts;328
16.2.4.1;14.2.4.1 Degradation as a Function of Contact Spacing;328
16.2.4.2;14.2.4.2 Degradation as a Function of Stress Power;328
16.2.4.3;14.2.4.3 Temperature Dependence and Activation Energy;330
16.2.4.4;14.2.4.4 Failure Mechanisms;332
16.2.5;14.2.5 Conclusions;334
16.3;14.3 Intrinsic Reliability of MISHEMT Gate Dielectrics;334
16.3.1;14.3.1 Introduction;334
16.3.2;14.3.2 Experiments;335
16.3.3;14.3.3 Analysis of Leakage Current Under Forward Bias Condition;336
16.3.4;14.3.4 Analysis of Leakage Current Under Reverse Bias Condition;339
16.3.5;14.3.5 Analysis of Defect States in Bulk SiN;340
16.3.6;14.3.6 TDDB Study;340
16.3.7;14.3.7 Conclusions;343
16.4;14.4 Buffer Stack Reliability—Off-State High-Voltage Drain Stress;343
16.4.1;14.4.1 Introduction;343
16.4.2;14.4.2 Current Conduction Mechanism;344
16.4.3;14.4.3 High-Temperature Reverse Bias;344
16.4.4;14.4.4 High-Voltage off-State Drain Stress;346
16.4.5;14.4.5 Conclusions;347
16.5;References;348
17;15 Switching Characteristics of Gallium Nitride Transistors: System-Level Issues;350
17.1;15.1 Switching Characteristics of E-mode and Cascode GaN;351
17.1.1;15.1.1 Switching Loss Mechanism;351
17.1.2;15.1.2 Packaging Influence;352
17.1.3;15.1.3 Comparison Between Hard Switching and Soft Switching;356
17.2;15.2 Special Issues of Cascode GaN;357
17.2.1;15.2.1 Impact of Packaging on Gate Breakdown;357
17.2.2;15.2.2 Impact of Capacitor Mismatch;358
17.2.2.1;15.2.2.1 Si Avalanche;358
17.2.2.2;15.2.2.2 Failure to Achieve ZVS;360
17.2.2.3;15.2.2.3 Divergent Oscillation;361
17.2.2.4;15.2.2.4 Solution to Solve Capacitor Mismatch Issue;363
17.3;15.3 Gate Driver Design for GaN Device;364
17.3.1;15.3.1 The di/dt Issue;364
17.3.2;15.3.2 The dv/dt Issue;365
17.4;15.4 System-Level Impact;368
17.4.1;15.4.1 3D Integrated Point-of-Load Converter;368
17.4.2;15.4.2 Isolated DC/DC Converter;371
17.4.2.1;15.4.2.1 48–12 V DCX;371
17.4.2.2;15.4.2.2 400–12 V DCX;372
17.4.3;15.4.3 MHz Totem-Pole PFC Rectifier;374
17.4.4;15.4.4High-Density Wall Adapter;377
17.5;15.5 Summary;378
17.6;References;379
18;Author index;381
19;Subject index;382