Marwedel Embedded System Design

1. Auflage 2006
ISBN: 978-0-387-30087-0
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 241 Seiten

Until the late eighties, information processing was associated with large mainframe computers and huge tape drives. During the nineties, this trend shifted towards information processing with personal computers, or PCs. The trend towards miniaturization continues. In the future, most of the information processing systems will be quite small and embedded into larger products such as transportation and fabrication equipment. Hence, these kinds of systems are called embedded systems. It is expected that the total market volume of embedded systems will be significantly larger than that of traditional information processing systems such as PCs and mainframes. Embedded systems share a number of common characteristics. For example, they must be dependable, efficient, meet real-time constraints and require customized user interfaces (instead of generic keyboard and mouse interfaces). Therefore, it makes sense to consider common principles of embedded system design. Embedded System Design  starts with an introduction into the area and a survey of specification languages for embedded systems. A brief overview is provided of hardware devices used for embedded systems and also presents the essentials of software design for embedded systems. Real-time operating systems and real-time scheduling are covered briefly. Techniques for implementing embedded systems are also discussed, using hardware/software codesign. It closes with a survey on validation techniques. Embedded System Design can be used as a text book for courses on embedded systems and as a source which provides pointers to relevant material in the area for PhD students and teachers. The book assumes a basic knowledge of information processing hardware and software.

Dr. Peter Marwedel received his PhD in Physics from the University of Kiel in 1974. He is one of the early researchers in high level synthesis, working on the MIMOLA system for a number of years. Dr. Marwedel is a professor at the University of Dortmund since 1989. He has served as the chairman of the computer science department, has played a leading role in establishing the Design, Automation and Test in Europe (DATE) conference and is the chairman of the Informatik Centrum Dortmund (ICD), a technology transfer centre.

Autoren/Hrsg.

Marwedel, Peter

Inhaltsverzeichnis

1;Contents;6
2;Preface;11
2.1;Importance of embedded systems;11
2.2;Audience for this book;12
2.3;Curriculum integration of embedded systems;12
3;Acknowledgments;15
4;Chapter 1 INTRODUCTION;16
4.1;1.1 Terms and scope;16
4.2;1.2 Application areas;20
4.3;1.3 Growing importance of embedded systems;23
4.4;1.4 Structure of this book;24
5;Chapter 2 SPECIFICATIONS;27
5.1;2.1 Requirements;27
5.2;2.2 Models of computation;30
5.3;2.3 StateCharts;32
5.3.1;2.3.1 Modeling of hierarchy;33
5.3.2;2.3.2 Timers;37
5.3.3;2.3.3 Edge labels and StateCharts semantics;38
5.3.4;2.3.4 Evaluation and extensions;40
5.4;2.4 General language characteristics;41
5.4.1;2.4.1 Synchronous and asynchronous languages;41
5.4.2;2.4.2 Process concepts;42
5.4.3;2.4.3 Synchronization and communication;42
5.4.4;2.4.4 Specifying timing;43
5.4.5;2.4.5 Using non-standard I/O devices;44
5.5;2.5 SDL;44
5.6;2.6 Petri nets ;50
5.6.1;2.6.1 Introduction;50
5.6.2;2.6.2 Condition/event nets;54
5.6.3;2.6.3 Place/transition nets;54
5.6.4;2.6.4 Predicate/transition nets;56
5.6.5;2.6.5 Evaluation;58
5.7;2.7 Message Sequence Charts;58
5.8;2.8 UML;59
5.9;2.9 Process networks ;64
5.9.1;2.9.1 Task graphs;64
5.9.2;2.9.2 Asynchronous message passing;67
5.9.3;2.9.3 Synchronous message passing;69
5.10;2.10 Java;72
5.11;2.11 VHDL ;73
5.11.1;2.11.1 Introduction;73
5.11.2;2.11.2 Entities and architectures;74
5.11.3;2.11.3 Multi-valued logic and IEEE 1164;76
5.11.4;2.11.4 VHDL processes and simulation semantics;83
5.12;2.12 SystemC;87
5.13;2.13 Verilog and SystemVerilog;89
5.14;2.14 SpecC;90
5.15;2.15 Additional languages;91
5.16;2.16 Levels of hardware modeling;93
5.17;2.17 Language comparison;96
5.18;2.18 Dependability requirements;97
6;Chapter 3 EMBEDDED SYSTEM HARDWARE;100
6.1;3.1 Introduction;100
6.2;3.2 Input ;101
6.2.1;3.2.1 Sensors;101
6.2.2;3.2.2 Sample-and-hold circuits;103
6.2.3;3.2.3 A/D-converters;104
6.3;3.3 Communication;106
6.3.1;3.3.1 Requirements;107
6.3.2;3.3.2 Electrical robustness;108
6.3.3;3.3.3 Guaranteeing real-time behavior;109
6.3.4;3.3.4 Examples;110
6.4;3.4 Processing Units ;111
6.4.1;3.4.1 Overview;111
6.4.2;3.4.2 Application-Speci.c Circuits (ASICs);113
6.4.3;3.4.3 Processors;113
6.4.4;3.4.4 Recon.gurable Logic;128
6.5;3.5 Memories;131
6.6;3.6 Output;133
6.6.1;3.6.1 D/A-converters;134
6.6.2;3.6.2 Actuators;135
7;Chapter 4 STANDARD SOFTWARE: EMBEDDED OPERATING SYSTEMS, MIDDLEWARE, AND SCHEDULING;137
7.1;4.1 Prediction of execution times;138
7.2;4.2 Scheduling in real-time systems;139
7.2.1;4.2.1 Classi.cation of scheduling algorithms;140
7.2.2;4.2.2 Aperiodic scheduling;143
7.2.3;4.2.3 Periodic scheduling;147
7.2.4;4.2.4 Resource access protocols;152
7.3;4.3 Embedded operating systems ;155
7.3.1;4.3.1 General requirements;155
7.3.2;4.3.2 Real-time operating systems;156
7.4;4.4 Middleware ;160
7.4.1;4.4.1 Real-time data bases;160
7.4.2;4.4.2 Access to remote objects;161
8;Chapter 5 IMPLEMENTING EMBEDDED SYSTEMS: HARDWARE/SOFTWARE CODESIGN;163
8.1;5.1 Task level concurrency management;165
8.2;5.2 High-level optimizations;169
8.2.1;5.2.1 Floating-point to .xed-point conversion;169
8.2.2;5.2.2 Simple loop transformations;171
8.2.3;5.2.3 Loop tiling/blocking;172
8.2.4;5.2.4 Loop splitting;175
8.2.5;5.2.5 Array folding;177
8.3;5.3 Hardware/software partitioning ;179
8.3.1;5.3.1 Introduction;179
8.3.2;5.3.2 COOL;180
8.4;5.4 Compilers for embedded systems ;189
8.4.1;5.4.1 Introduction;189
8.4.2;5.4.2 Energy-aware compilation;190
8.4.3;5.4.3 Compilation for digital signal processors;193
8.4.4;5.4.4 Compilation for multimedia processors;196
8.4.5;5.4.5 Compilation for VLIW processors;196
8.4.6;5.4.6 Compilation for network processors;197
8.4.7;5.4.7 Compiler generation, retargetable compilers and design space exploration;197
8.5;5.5 Voltage Scaling and Power Management ;198
8.5.1;5.5.1 Dynamic Voltage Scaling;198
8.5.2;5.5.2 Dynamic power management (DPM);201
8.6;5.6 Actual design .ows and tools ;202
8.6.1;5.6.1 SpecC methodology;202
8.6.2;5.6.2 IMEC tool .ow;203
8.6.3;5.6.3 The COSYMA design .ow;206
8.6.4;5.6.4 Ptolemy II;207
8.6.5;5.6.5 The OCTOPUS design .ow;208
9;Chapter 6 VALIDATION;210
9.1;6.1 Introduction;210
9.2;6.2 Simulation;211
9.3;6.3 Rapid Prototyping and Emulation;212
9.4;6.4 Test ;212
9.4.1;6.4.1 Scope;212
9.4.2;6.4.2 Design for testability;213
9.4.3;6.4.3 Self-test programs;216
9.5;6.5 Fault simulation;217
9.6;6.6 Fault injection;218
9.7;6.7 Risk- and dependability analysis;218
9.8;6.8 Formal Veri.cation;220
10;References;223
11;List of Figures;239
12;Index;246

Leseproben

Chapter 2
SPECIFICATIONS (p. 13-14)

2.1 Requirements
Consistent with the simplified design flow (see .g. 1.5), we will now describe requirements and approaches for specifying embedded systems. There may still be cases in which the specification of embedded systems is captured in a natural language, such as English. However, this approach is absolutely inappropriate since it lacks key requirements for specification techniques: it is necessary to check specifications for completeness, absence of contradictions and it should be possible to derive implementations from the speci.cation in a systematic way. Therefore, specifications should be captured in machine readable, formal languages. Specification languages for embedded systems should be capable of representing the following features: Hierarchy: Human beings are generally not capable of comprehending systems that contain many objects (states, components) having complex relations with each other. The description of all real-life systems needs more objects than human beings can understand. Hierarchy is the only mechanism that helps to solve this dilemma. Hierarchies can be introduced such that humans need to handle only a small number of objects at any time.

There are two kinds of hierarchies:

– Behavioral hierarchies: Behavioral hierarchies are hierarchies containing objects necessary to describe the system behavior. States, events and output signals are examples of such objects.

– Structural hierarchies: Structural hierarchies describe how systems are composed of physical components.

For example, embedded systems can be comprised of processors, memories, actors and sensors. Processors, in turn, include registers, multiplexers and adders. Multiplexers are composed of gates.

Timing-behavior: Since explicit timing requirements are one of the characteristics of embedded systems, timing requirements must be captured in the specification.

State-oriented behavior: It was already mentioned in chapter 1 that automata provide a good mechanism for modeling reactive systems. Therefore, the state-oriented behavior provided by automata should be easy to describe. However, classical automata models are insufficient, since they cannot model timing and since hierarchy is not supported.

Event-handling: Due to the reactive nature of embedded systems, mechanisms for describing events must exist. Such events may be external events (caused by the environment) or internal events (caused by components of the system).

No obstacles to the generation of efficient implementations: Since embedded systems have to be ef.cient, no obstacles prohibiting the generation of ef.cient realizations should be present in the specification.

Support for the design of dependable systems: Specification techniques should provide support for designing dependable systems. For example, specification languages should have unambiguous semantics, facilitate formal veri.cation and be capable of describing security and safety requirements.

Exception-oriented behavior: In many practical, systems exceptions do occur. In order to design dependable systems, it must be possible to describe actions to handle exceptions easily. It is not acceptable that exceptions have to be indicated for each and every state (like in the case of classical state diagrams). Example: In .g. 2.1, input k might correspond to an exception.

Specifying this exception at each state makes the diagram very complex. The situation would get worse for larger state diagrams with many transitions. We will later show, how all the transitions can be replaced by a single one.