Buch, Englisch, 136 Seiten, Format (B × H): 163 mm x 244 mm, Gewicht: 384 g
Buch, Englisch, 136 Seiten, Format (B × H): 163 mm x 244 mm, Gewicht: 384 g
Reihe: Analog Circuits and Signal Processing
ISBN: 978-90-481-9715-6
Verlag: Springer
The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature.
Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
Zielgruppe
Research
Autoren/Hrsg.
Fachgebiete
Weitere Infos & Material
1. Introduction. – 2. Time-interleaved Track and Holds.- 3. Sub-ADC architectures for time-interleaved ADCs. – 4. Implementation of a high-speed time-interleaved ADC. – 5. Summary and conclusions.