Lin / Kao / Kuo VLSI Design for Video Coding

H.264/AVC Encoding from Standard Specification to Chip
1. Auflage 2009
ISBN: 978-1-4419-0959-6
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 176 Seiten

High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing. This book will present VLSI architectural design and chip implementation for high definition H.264/AVC video encoding, using a state-of-the-art video application, with complete VLSI prototype, via FPGA/ASIC. It will serve as an invaluable reference for anyone interested in VLSI design and high-level (EDA) synthesis for video.

Autoren/Hrsg.

Lin, Youn-Long Steve

Kao, Chao-Yang

Kuo, Hung-Chih

Chen, Jian-Wen

Inhaltsverzeichnis

1;Preface;5
2;Contents;7
3;1 Introduction to Video Coding and H.264/AVC;10
3.1;1.1 Introduction;10
3.1.1;1.1.1 Basic Coding Unit;11
3.1.2;1.1.2 Video Encoding Flow;11
3.1.3;1.1.3 Color Space Conversion;11
3.1.4;1.1.4 Prediction of a Macroblock;12
3.1.5;1.1.5 Intraframe Prediction;13
3.1.6;1.1.6 Interframe Prediction;13
3.1.7;1.1.7 Motion Vector;13
3.1.8;1.1.8 Prediction Error;13
3.1.9;1.1.9 Space-Domain to Frequency-Domain Transformation of Residual Error;14
3.1.10;1.1.10 Coefficient Quantization;14
3.1.11;1.1.11 Reconstruction;14
3.1.12;1.1.12 Motion Compensation;14
3.1.13;1.1.13 Deblocking Filtering;15
3.2;1.2 Book Organization;15
4;2 Intra Prediction;19
4.1;2.1 Introduction;19
4.1.1;2.1.1 Algorithm;20
4.1.2;2.1.2 Design Consideration;24
4.2;2.2 Related Works;27
4.2.1;2.2.1 Prediction Time Reduction Approaches;27
4.2.2;2.2.2 Hardware Area Reduction Approaches;27
4.3;2.3 A VLSI Design for Intra Prediction;28
4.3.1;2.3.1 Subtasks Scheduling;28
4.3.2;2.3.2 Architecture;32
4.3.2.1;2.3.2.1 RL Engine;33
4.3.2.2;2.3.2.2 Non-RL Engine;33
4.3.3;2.3.3 Evaluation;38
4.4;2.4 Summary;38
5;3 Integer Motion Estimation;39
5.1;3.1 Introduction;39
5.1.1;3.1.1 Algorithms;41
5.1.2;3.1.2 Design Considerations;44
5.2;3.2 Related Works;45
5.2.1;3.2.1 Architecture;45
5.2.2;3.2.2 Data-Reuse Schemes;51
5.3;3.3 A VLSI Design for Integer Motion Estimation;52
5.3.1;3.3.1 Proposed Data-Reuse Scheme;53
5.3.2;3.3.2 Architecture;55
5.3.3;3.3.3 Data Flow;57
5.3.4;3.3.4 Evaluation;60
5.4;3.4 Summary;61
6;4 Fractional Motion Estimation;64
6.1;4.1 Introduction;64
6.1.1;4.1.1 Algorithms;65
6.1.2;4.1.2 Design Considerations;68
6.2;4.2 Related Works;68
6.3;4.3 A VLSI Design for Fractional Motion Estimation;70
6.3.1;4.3.1 Proposed Architecture;70
6.3.2;4.3.2 Proposed Resource Sharing Methodfor SATD Generator;75
6.3.2.1;4.3.2.1 Analysis of SATD Generator Usage;75
6.3.2.2;4.3.2.2 Customized Arbitration Scheme;76
6.3.3;4.3.3 Evaluation;79
6.4;4.4 Summary;79
7;5 Motion Compensation;80
7.1;5.1 Introduction;80
7.1.1;5.1.1 Algorithms;80
7.1.2;5.1.2 Design Considerations;82
7.2;5.2 Related Works;82
7.2.1;5.2.1 Memory Traffic Reduction;83
7.2.2;5.2.2 Interpolation Engine;83
7.3;5.3 A VLSI Design for Motion Compensation;84
7.3.1;5.3.1 Motion Vector Generator;84
7.3.2;5.3.2 Interpolator;86
7.3.2.1;5.3.2.1 Interpolation Engine;87
7.3.2.2;5.3.2.2 Area-Efficient Chroma Filter;88
7.3.2.3;5.3.2.3 Fully Utilized Weighted Prediction Engine;88
7.3.3;5.3.3 Evaluation;90
7.4;5.4 Summary;90
8;6 Transform Coding;91
8.1;6.1 Introduction;91
8.1.1;6.1.1 Algorithms;91
8.1.1.1;6.1.1.1 Transform;95
8.1.1.2;6.1.1.2 Quantization;96
8.1.1.3;6.1.1.3 Inverse Quantization;97
8.1.1.4;6.1.1.4 Inverse Transform;98
8.1.1.5;6.1.1.5 Run Level Coding;99
8.1.1.6;6.1.1.6 Encoding Process of the Transform Coding Unit;100
8.1.2;6.1.2 Design Consideration;103
8.2;6.2 Related Works;103
8.2.1;6.2.1 Multitransform Engine Approaches;103
8.2.2;6.2.2 Trans/Quan or InvQuan/InvTrans Integration Approaches;103
8.3;6.3 A VLSI Design for Transform Coding;104
8.3.1;6.3.1 Subtasks Scheduling;104
8.3.2;6.3.2 Architecture;104
8.3.2.1;6.3.2.1 Multitransform Engine;105
8.3.2.2;6.3.2.2 Combined Q/IQ Engine;106
8.3.2.3;6.3.2.3 RLC Engine;107
8.3.2.4;6.3.2.4 Organization of the Coefficient Memory;108
8.3.3;6.3.3 Evaluation;112
8.4;6.4 Summary;112
9;7 Deblocking Filter;113
9.1;7.1 Introduction;113
9.1.1;7.1.1 Deblocking Filter Algorithm;114
9.1.1.1;7.1.1.1 Filtering Order;114
9.1.1.2;7.1.1.2 Boundary Strength, Thresholds, and FilterSampleflag;115
9.1.1.3;7.1.1.3 Edge Filter;118
9.1.2;7.1.2 Subtasks Processing Order;118
9.1.3;7.1.3 Design Considerations;119
9.1.3.1;7.1.3.1 Processing Cycles;120
9.1.3.2;7.1.3.2 External Memory Traffic;120
9.1.3.3;7.1.3.3 Working Frequency;120
9.1.3.4;7.1.3.4 Hardware Cost;120
9.1.3.5;7.1.3.5 Skip Mode Support for Eliminating Unnecessary Filtering;121
9.2;7.2 Related Works;121
9.3;7.3 A VLSI Design for Deblocking Filter;122
9.3.1;7.3.1 Subtasks Scheduling;122
9.3.2;7.3.2 Architecture;122
9.3.2.1;7.3.2.1 Filtering Order;124
9.3.2.2;7.3.2.2 Memory Organization;125
9.3.2.3;7.3.2.3 Two-Result-Per-Cycle Edge Filter;125
9.3.2.4;7.3.2.4 Pixels Transfer of a Non-skip-all MB;127
9.3.3;7.3.3 Evaluation;128
9.4;7.4 Summary;130
10;8 CABAC Encoder;131
10.1;8.1 Introduction;131
10.1.1;8.1.1 CABAC Encoder Algorithm;131
10.1.1.1;8.1.1.1 Building Context Table;132
10.1.1.2;8.1.1.2 Binarization Schemes;132
10.1.1.3;8.1.1.3 Context Modeler;135
10.1.1.4;8.1.1.4 Binary Arithmetic Encoder;136
10.1.1.5;8.1.1.5 CABAC Encoding Flow;138
10.1.2;8.1.2 Subtasks Processing Order ;140
10.1.3;8.1.3 Design Consideration;140
10.2;8.2 Related Works;142
10.3;8.3 A VLSI Design for CABAC Encoder;145
10.3.1;8.3.1 Subtasks Scheduling;145
10.3.2;8.3.2 Architecture;146
10.3.2.1;8.3.2.1 BCMODS Generation for Sig_coeff_flag and Last_sig_coeff_flag Types;147
10.3.2.2;8.3.2.2 BCMODS Generation for Coeff_level Type;147
10.3.2.3;8.3.2.3 BCMODS Generation for CBF Type;148
10.3.2.4;8.3.2.4 BCMODS Generation for MVD Type;149
10.3.2.5;8.3.2.5 Pipelined Multibin BAE Architecture;149
10.3.3;8.3.3 Evaluation;153
10.4;8.4 Summary;154
11;9 System Integration;157
11.1;9.1 Introduction;157
11.1.1;9.1.1 Algorithm;157
11.1.2;9.1.2 Design Consideration;159
11.2;9.2 Related Works;161
11.3;9.3 A VLSI Design for H.264/AVC Encoder;162
11.3.1;9.3.1 Subtasks Scheduling;162
11.3.2;9.3.2 Architecture;165
11.3.2.1;9.3.2.1 Encoder Core;166
11.3.2.2;9.3.2.2 AMBA Interface;168
11.3.3;9.3.3 Evaluation;171
11.4;9.4 Summary;172
12;References;173
13;Index;178