Lee Learning from VLSI Design Experience

1. Auflage 2019
ISBN: 978-3-030-03238-8
Verlag: Springer International Publishing
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 229 Seiten, eBook

This book shares with readers practical design knowledge gained from the author’s 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their workarounds.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Lee, Weng Fook

Inhaltsverzeichnis

1;Dedication;5
2;Preface;6
3;Trademarks;9
4;Acknowledgment;10
5;Contents;11
6;List of Figures;14
7;List of Tables;20
8;List of Examples;21
9;Chapter 1: Introduction;24
10;Chapter 2: Design Methodology and Flow;25
10.1;Analog/Custom Design Flow;25
10.2;Digital Design Flow (Fig. 2.7);29
10.3;Synthesis;51
10.4;Standard Cell Library;51
10.5;Design Constraints;53
10.5.1;Input Delay;54
10.5.2;Output Delay;54
10.5.3;Path Delay;55
10.5.4;Clock Specification;55
10.5.5;Multicycle Path;56
10.5.6;False Path;57
10.6;Synthesis Optimizations to Improve Timing;57
10.7;Importance of Clock in Backend;60
10.7.1;Floor Plan;61
10.7.2;Clock Tree Synthesis;65
11;Chapter 3: Multiple Clock Design;67
11.1;Mean Time Between Failure;68
11.2;Synchronizer;71
11.2.1;Receiving Clock Faster than Transmitting Clock;71
11.2.2;Transmitting Clock Faster than Receiving Clock;74
11.3;Reset;84
12;Chapter 4: Latch Inference;88
12.1;If-Else Statement;89
12.2;Case Statement;91
13;Chapter 5: Design for Test;93
13.1;Scan Chain;94
13.2;Before Scan;94
13.3;After Scan;97
13.4;Automatic Test Pattern Generation (ATPG);98
13.4.1;Test Compression;99
13.5;Scan Chain Crossing Different Clock Domains During Shift Phase of ATPG;102
13.6;Scan Chain for Design with Different Power Domains;109
13.7;Capture Phase of ATPG for Multiple Clock Design;111
13.8;Logic Built in Self-Test;113
13.8.1;How Does Logic BIST Work;113
13.8.2;Implementation of Logic BIST;114
13.9;Memory BIST;123
14;Chapter 6: Signed Verilog;130
14.1;Mixing Signed and Unsigned;130
14.2;Multiplication and Division of Signed and Unsigned Values;136
14.2.1; Unsigned Shifting in Verilog;138
14.2.2;Signed Shifting in Verilog;141
14.2.3;Rounding Down Due to Signed Shift Right;144
14.2.4;Simulating RTL Using Signed and Unsigned;146
15;Chapter 7: State Machine;149
15.1;RTL Verilog for a State Machine;149
15.1.1;RTL Coding Style for State Machine Using Two Always Processes;156
15.2;Different RTL Coding Styles for State Machine;156
15.3;When to Use One-Hot, Gray, or Binary Encoding;166
15.4;Blocking Statements;167
15.5;Non-blocking Statements;170
15.6;Rule of Thumb when Using Non-blocking Statement and Blocking Statement;173
16;Chapter 8: RTL Coding Guideline;176
16.1;Contention;176
16.2;Sensitivity List;178
16.3;Level-Sensitive and Edge-Sensitive RTL;181
16.3.1;Edge-Sensitive RTL Verilog Code;181
16.3.2;Level-Sensitive RTL Verilog Code;184
16.3.3;Mixing Level-Sensitive and Edge-Sensitive Verilog Code;185
16.4;Input, Output, and Bidirectional Ports in RTL;186
16.5;Blocking and Non-blocking Statement;186
16.6;Inferred Latch;187
16.7;Signed and Unsigned;187
16.8;Logic between Blocks;187
16.9;Register Output of Blocks;188
16.10;Naming Convention;190
17;Chapter 9: Code Coverage;192
17.1;Flow for Code Coverage;192
17.2;Types of Code Coverage;193
17.3;Simulation with Code Coverage;194
17.4;Enhancing Testbench to Increase Code Coverage;212
18;References;227
19;Index;228

Über Autor(innen)

Weng Fook Lee is a distinguished Technical Director at Emerald Systems Design Center with 25 years of IC Design experience. Lee has vast experience in designing with Verilog and VHDL, and is an internationally acknowledged expert in the field of RTL coding and logic synthesis for ASIC/FPGA/SOC. Lee is an expert in synthesizing and tweaking synthesis for performance and low power, leading enhanced methodology to address advanced DFT techniques for VDSM technology, development and deployment of low power standard cell libraries. Lee have lead the development of new architectures and micro-architectures for efficient PMSM motion control ASIC and have developed architectures for AI classification algorithms implementation in ASIC. Lee published“VHDL Coding and Logic Synthesis with Synopsys" with Academic Press Publication, US (ISBN: 0-12-440651-3) in May 2000, "Verilog Coding for Logic Synthesis" with John Wiley Publication, US (ISBN: 0-471-42976-7) in April 2003, “VLIW Microprocessor Hardware Design for ASICs and FPGA” with McGraw Hill Publication, US (ISBN: 978-0071497022) in Aug 2007. Lee is also the inventor and co-inventor of 14 design patents granted by the US Patent and Trademark Office.