Kuon / Rose Quantifying and Exploring the Gap Between FPGAs and ASICs

1. Auflage 2010
ISBN: 978-1-4419-0739-4
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 180 Seiten

Field-programmable gate arrays (FPGAs), which are pre-fabricated, programmable digital integrated circuits (ICs), provide easy access to state-of-the-art integrated circuit process technology, and in doing so, democratize this technology of our time. This book is about comparing the qualities of FPGA - their speed performance, area and power consumption, against custom-fabricated ICs, and exploring ways of mitigating their de ciencies. This work began as a question that many have asked, and few had the resources to answer - how much worse is an FPGA compared to a custom-designed chip? As we dealt with that question, we found that it was far more dif cult to answer than we anticipated, but that the results were rich basic insights on fundamental understandings of FPGA architecture. It also encouraged us to nd ways to leverage those insights to seek ways to make FPGA technology better, which is what the second half of the book is about. While the question 'How much worse is an FPGA than an ASIC?' has been a constant sub-theme of all research on FPGAs, it was posed most directly, some time around May 2004, by Professor Abbas El Gamal from Stanford University to us - he was working on a 3D FPGA, and was wondering if any real measurements had been made in this kind of comparison. Shortly thereafter we took it up and tried to answer in a serious way.

Autoren/Hrsg.

Kuon, Ian

Rose, Jonathan

Inhaltsverzeichnis

1;Preface;5
2;Contents;6
3;Acronyms;9
4;Introduction;10
4.1;Measuring the FPGA to ASIC Gap;11
4.2;Navigating the Gap;12
4.3;Organization;13
5;Background;14
5.1;FPGA Architecture;14
5.1.1;Logic Block Architecture;14
5.1.1.1;Logic Block Architecture of the Altera Stratix II;16
5.1.2;Routing Architecture;18
5.1.3;Heterogeneity;21
5.2;FPGA Circuit Design;22
5.3;FPGA Transistor Sizing;25
5.4;FPGA Assessment Methodology;26
5.4.1;FPGA CAD Flow;26
5.4.2;Area Model;27
5.4.3;Performance Measurement;29
5.5;Automated Transistor Sizing;29
5.5.1;Static Transistor Sizing;30
5.5.2;Dynamic Sizing;32
5.5.3;Hybrid Approaches to Sizing;32
5.5.4;FPGA-Specific Sizing;33
5.6;FPGA to ASIC Gap;33
6;Measuring the Gap;36
6.1;Comparison Methodology;37
6.1.1;Benchmark Circuit Selection;37
6.2;FPGA CAD Flow;40
6.3;ASIC CAD Flow;41
6.3.1;ASIC Synthesis;41
6.3.2;ASIC Placement and Routing;44
6.3.3;Extraction and Timing Analysis;45
6.4;Comparison Metrics;45
6.4.1;Area;45
6.4.2;Delay;46
6.4.3;Power;46
6.4.3.1;Dynamic and Static Power Measurement;47
6.4.3.2;Dynamic and Static Power Comparison Methodology;48
6.5;Measurement Results;48
6.5.1;Area;49
6.5.1.1;Approximate Bounds;52
6.5.1.2;Impact of Benchmark Size on FPGA Area Measurements;54
6.5.1.3;Other Considerations;56
6.5.2;Delay;58
6.5.2.1;Speed Grades;62
6.5.2.2;Retiming and Heterogeneous Blocks;63
6.5.3;Dynamic Power Consumption;64
6.5.3.1;Other Considerations;67
6.5.4;Static Power Consumption;67
6.6;Summary;70
7;Automated Transistor Sizing for FPGAs;72
7.1;Uniqueness of FPGA Transistor Sizing Problem;73
7.1.1;Programmability;73
7.1.2;Repetition;73
7.2;Optimization Tool Inputs;74
7.2.1;Logical Architecture Parameters;74
7.2.2;Electrical Architecture Parameters;75
7.2.3;Optimization Objective;76
7.3;Optimization Metrics;77
7.3.1;Area Model;77
7.3.2;Performance Modelling;80
7.4;Optimization Algorithm;82
7.4.1;Phase 1: Switch-Level Transistor Models;83
7.4.1.1;Switch-Level Transistor Models;83
7.4.1.2;TILOS-based algorithm;86
7.4.1.3;Termination Criteria;87
7.4.2;Phase 2: Sizing with Accurate Models;88
7.4.2.1;Parameter Grouping;90
7.4.2.2;Parameter Ordering;91
7.5;Quality of Results;91
7.5.1;Comparison with Past Routing Optimizations;91
7.5.2;Comparison with Past Logic Block Optimization;93
7.5.3;Comparison to Exhaustive Search;98
7.5.4;Optimizer Run Time;99
7.6;Summary;99
8;Navigating the Gap Using Architecture and Process Technology Scaling;100
8.1;Area and Performance Measurement Methodology;101
8.1.1;Performance Measurement;101
8.1.2;Area Measurement;103
8.2;Impact of Logical Architectures on Area and Performance;104
8.3;Impact of Process Technology Scaling on Area and Performance;107
8.4;Summary;110
9;Navigating the Gap using Transistor Sizing;112
9.1;Transistor-Sizing Trade-offs;113
9.2;Definition of ``Interesting'' Trade-offs;115
9.3;Trade-Offs with Transistor Sizing and Architecture;118
9.3.1;Impact of Elasticity Threshold Factor;120
9.4;Logical Architecture Trade-offs;121
9.4.1;LUT Size;122
9.4.2;Cluster Size;123
9.4.3;Segment Length;124
9.5;Circuit Structure Trade-offs;124
9.5.1;Buffer Positioning;125
9.5.2;Multiplexer Implementation;127
9.5.2.1;General Multiplexer Design Analysis;127
9.5.2.2;Area--Delay Trade-Offs Using Varied Multiplexer Designs;129
9.6;Trade-offs and the Gap;131
9.6.1;Comparison with Commercial Families;133
9.7;Summary;134
10;Conclusions and Future Work;135
10.1;Knowledge Gained;135
10.2;Future Potential Research Directions;136
10.2.1;Measuring the Gap;136
10.2.2;Navigating the Gap;138
10.3;Concluding Remarks;139
11;FPGA to ASIC Comparison Details;140
11.1;Benchmark Information;140
11.2;FPGA to ASIC Comparison Data;140
12;Representative Delay Weighting;147
12.1;Benchmark Statistics;147
12.1.1;LUT Usage;148
12.2;Representative Delay Weights;150
13;Multiplexer Implementations;153
13.1;Multiplexer Designs;153
13.2;Evaluation of Multiplexer Designs;155
14;Architectures Used for Area and Delay Range Investigation;160
15;Logical Architecture to Transistor Sizing Process;163
16;Index;181