Creating Assertion-Based IP

1. Auflage. Softcover version of original hardcover Auflage 2008
ISBN: 978-1-4419-4218-0
Verlag: Springer US

Buch, Englisch, 318 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 511 g

Reihe: Integrated Circuits and Systems

This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. It demonstrates a systematic process for formal specification and formal testplanning, and also demonstrates effective use of assertions languages beyond the traditional language construct discussions

Note that there many books published on assertion languages (such as SystemVerilog assertions and PSL). Yet, none of them discuss the important process of testplanning and using these languages to create verification IP. This is the first book published on this subject.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Krolnik, Adam C.

Foster, Harry D.

Fachgebiete

• Technische Wissenschaften Technik Allgemein Computeranwendungen in der Technik
• Mathematik | Informatik EDV | Informatik Angewandte Informatik Computeranwendungen in Wissenschaft & Technologie
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Geisteswissenschaften Design Produktdesign, Industriedesign

Inhaltsverzeichnis

Definitions and Terminology.- The Process.- Bus-Based Design Example.- Interfaces.- Arbiters.- Controllers.- Datapath.