Kong / Overhauser Digital Timing Macromodeling for VLSI Design Verification

Erscheinungsjahr 2012
ISBN: 978-1-4615-2321-5
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 319, 265 Seiten, eBook

Reihe: The Springer International Series in Engineering and Computer Science

Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.

Zielgruppe

Research

Autoren/Hrsg.

Kong, Jeong-Taek

Overhauser, David V.

Inhaltsverzeichnis

1 Introduction.- 1.1 Overview of the VLSI Design and Verification Process.- 1.2 Problems in MOS Digital Macromodeling.- 1.3 Contributions of The New Macromodel.- 2 Survey of Simulation and Macromodeling Techniques.- 2.1 Introduction.- 2.2 Circuit Simulation.- 2.3 Macromodeling.- 2.4 Gate-level and Switch-level Simulation.- 2.5 Switch-level Timing Simulation.- 2.6 Fast-timing Simulation.- 2.7 Interconnection Analysis.- 2.8 Mixed-mode/Mixed-domain Simulation.- 3 A Nonlinear Macromodel.- 3.1 Introduction.- 3.2 A Macromodel for the General Case.- 3.3 Macromodeling with Fast Input Transitions.- 3.4 Slow Input and Fast Output Transitions.- 3.5 Experimental Results.- 4 Reduction Techniques for Complex Gates.- 4.1 Introduction.- 4.2 Reduction of Series-connected Transistors.- 4.3 Generalized Reduction Techniques for Complex Gates.- 4.4 Experimental Results.- 5 Accounting for RC-Interconnects.- 5.1 Introduction.- 5.2 Related Work.- 5.3 RC-interconnect Effects.- 5.4 Modeling the Effective Driver-loading.- 5.5 Driver Output Waveform Estimation.- 5.6 Experimental Results.- 6 Transmission Gate Modeling.- 6.1 Introduction.- 6.2 A Gate Driving a Transmission Gate.- 7 Conclusions.- 7.1 Summary.- 7.2 Future Research.- A The Spice Level 2 Model.- B Nonlinear Macromodel Output Response Derivations.- B.1 The Derivation of the Output Response in Region III.- B.2 The Derivation of the Output Response in Region VI.- D Delay Errors for Various AOI Gates.- References.