Integrated System-Level Modeling of Network-On-Chip Enabled Multi-Processor Platforms

2006. Auflage 2006
ISBN: 978-1-4020-4825-8
Verlag: Springer

Buch, Englisch, 186 Seiten, Format (B × H): 165 mm x 248 mm, Gewicht: 1060 g

Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models.

Zielgruppe

Research

Autoren/Hrsg.

Kogel, Tim

Leupers, Rainer

Meyr, Heinrich

Fachgebiete

• Technische Wissenschaften Technik Allgemein Computeranwendungen in der Technik
• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
• Mathematik | Informatik EDV | Informatik Programmierung | Softwareentwicklung Software Engineering Objektorientierte Softwareentwicklung
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Geisteswissenschaften Design Produktdesign, Industriedesign
• Mathematik | Informatik EDV | Informatik Programmierung | Softwareentwicklung Grafikprogrammierung
• Mathematik | Informatik EDV | Informatik Technische Informatik Systemverwaltung & Management
• Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
• Mathematik | Informatik EDV | Informatik Angewandte Informatik Computeranwendungen in Wissenschaft & Technologie
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Mathematik | Informatik EDV | Informatik Betriebssysteme Windows Betriebssysteme

Inhaltsverzeichnis

Foreword. Preface.

1. INTRODUCTION. 1.1 Organization of the Book Chapters.

2. EMBEDDED SOC APPLICATIONS. 2.1 Networking Domain. 2.2 Multimedia Domain. 2.3 Wireless Communications. 2.4 Application Trends. 2.5 First Order Application Partitioning.

3. CLASSIFICATION OF PLATFORM ELEMENTS. 3.1 Architecture Metrics. 3.2 Processing Elements. 3.3 On-Chip Communication. 3.4 Summary.

4. SYSTEM LEVEL DESIGN PRINCIPLES. 4.1 The Platform Based Design Paradigm. 4.2 Design Phases. 4.3 Abstraction Mechanisms. 4.4 Models of Computation. 4.5 Object versus Actor Oriented Design. 4.6 System Level Design Requirements.

5. RELATED WORK. 5.1 Traditional HW/SW Co-Design. 5.2 SystemC based Transaction Level Modeling. 5.3 Current Research on MP-SoC Design Methodologies. 5.4 Summary.

6. METHODOLOGY OVERVIEW. 6.1 Application Modeling. 6.2 Architecture Modeling. 6.3 Envisioned Design Flow. 6.4 MP-SoC Simulation Framework.

7. UNIFIED TIMING MODEL. 7.1 Tagged Signal Model Introduction. 7.2 Reactive Process Network. 7.3 Architecture Model. 7.4 Performance Metrics. 7.5 Summary.

8. MP-SOC SIMULATION FRAMEWORK. 8.1 The Generic Synchronization Protocol. 8.2 Generic VPU Model. 8.3 NoC Framework. 8.4 Tool Support. 8.5 Summary.

9. CASE STUDY. 9.1 IPv4 Forwarding with QoS Support. 9.2 Intel IXP2400 Reference NPU. 9.3 Custom IPv4 Platform. 9.4 Simulation Results.

10. SUMMARY.

Appendices. A The OSCI TLM Standard. B The OCPIP TL3 Channel. C The Architects View Framework.

List of Figures. List of Tables. References. Index.