Keliu / Sanchez-Sinencio CMOS PLL Synthesizers: Analysis and Design

1. Auflage 2006
ISBN: 978-0-387-23669-8
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 783, 216 Seiten

Reihe: The Springer International Series in Engineering and Computer Science

Thanks to the advance of semiconductor and communication technology, the wireless communication market has been booming in the last two decades. It evolved from simple pagers to emerging third-generation (3G) cellular phones. In the meanwhile, broadband communication market has also gained a rapid growth. As the market always demands hi- performance and low-cost products, circuit designers are seeking hi- integration communication devices in cheap CMOS technology. The phase-locked loop frequency synthesizer is a critical component in communication devices. It works as a local oscillator for frequency translation and channel selection in wireless transceivers and broadband cable tuners. It also plays an important role as the clock synthesizer for data converters in the analog-and-digital signal interface. This book covers the design and analysis of PLL synthesizers. It includes both fundamentals and a review of the state-of-the-art techniques. The transient analysis of the third-order charge-pump PLL reveals its locking behavior accurately. The behavioral-level simulation of PLL further clarifies its stability limit. Design examples are given to clearly illustrate the design procedure of PLL synthesizers. A complete derivation of reference spurs in the charge-pump PLL is also presented in this book. The in-depth investigation of the digital CA modulator for fractional-N synthesizers provides insightful design guidelines for this important block.

Autoren/Hrsg.

Shu, Keliu

Sanchez-Sinencio, Edgar

Inhaltsverzeichnis

1;Contents;6
2;List of Acronyms and Symbols;10
3;Preface;16
4;Chapter 1 INTRODUCTION;18
4.1;1.1 Motivation;18
4.2;1.2 Summary of book;19
4.3;1.3 Book organization;21
4.4;REFERENCES;22
5;Chapter 2 FREQUENCY SYNTHESIZER FOR WIRELESS APPLICATIONS;24
5.1;2.1 Definition and characteristics;24
5.2;2.2 Phase noise and timing jitter;25
5.2.1;2.2.1 Phase noise and spurious tone;25
5.2.2;2.2.2 Timing jitter;28
5.3;2.3 Implementations of frequency synthesizer;31
5.3.1;2.3.1 Direct analog frequency synthesizer;31
5.3.2;2.3.2 Direct digital frequency synthesizer;32
5.3.3;2.3.3 PLL-based frequency synthesizer;33
5.3.4;2.3.4 DLL-based frequency synthesizer;37
5.3.5;2.3.5 Hybrid frequency synthesizer;38
5.3.6;2.3.6 Summary and comparison of synthesizers;38
5.4;2.4 Frequency synthesizer for wireless transceivers;39
5.5;2.5 Other applications of PLL and frequency synthesizer;41
5.6;REFERENCES;43
6;Chapter 3 PLL FREQUENCY SYNTHESIZER;47
6.1;3.1 PLL frequency synthesizer basics;47
6.1.1;3.1.1 Basic building blocks of charge-pump PLL;47
6.1.2;3.1.2 Continuous-time linear phase analysis;50
6.1.3;3.1.3 Locking time;60
6.1.4;3.1.4 Tracking and acquisition;72
6.2;3.2 Fast-locking techniques;74
6.2.1;3.2.1 Bandwidth gear-shifting;74
6.2.2;3.2.2 VCO pre-tuning;76
6.3;3.3 Discrete-time analysis and nonlinear modeling;76
6.3.1;3.3.1 z-domain transfer function and stability analysis;76
6.3.2;3.3.2 Nonlinear dynamic behavior modeling;78
6.4;3.4 Design example: 2.4GHz integer-N PLL for Bluetooth;78
6.5;REFERENCES;81
7;Chapter 4 S. FRACTIONAL-N PLL SYNTHESIZER;85
7.1;4.1 S. fractional-N frequency synthesizer;85
7.1.1;4.1.1 S. quantization noise to phase noise mapping;86
7.1.2;4.1.2 S. quantization noise to timing jitter mapping;89
7.2;4.2 A Comparative study of digital S. modulators;89
7.2.1;4.2.1 Design considerations;89
7.2.2;4.2.2 Four types of digital S. modulators;90
7.2.3;4.2.3 Summary of comparative study;103
7.3;4.3 Other applications of S.-PLL;106
7.3.1;4.3.1 Direct digital modulation;106
7.3.2;4.3.2 Frequency-to-digital conversion;107
7.4;4.4 Modeling and simulation of S.-PLL;108
7.5;4.5 Design example: 900MHz S.-PLL for GSM;111
7.6;REFERENCES;114
8;Chapter 5 ENHANCED PHASE SWITCHING PRESCALER;118
8.1;5.1 Prescaler architecture;118
8.1.1;5.1.1 Conventional prescaler;118
8.1.2;5.1.2 Phase switching prescaler;120
8.1.3;5.1.3 Injection-locked prescaler;122
8.1.4;5.1.4 Summary and comparison of prescalers;122
8.2;5.2 Enhanced phase-switching prescaler;123
8.3;5.3 Circuit design and simulation results;125
8.3.1;5.3.1 Eight 45O-spaced phases generation;125
8.3.2;5.3.2 8-to-1 multiplexer;126
8.3.3;5.3.3 Switching control circuit;127
8.3.4;5.3.4 Asynchronous frequency divider;128
8.4;5.4 Delay budget in the switching control loop;130
8.5;5.5 Spurs due to nonidea14S0 phase spacing;132
8.6;REFERENCES;138
9;Chapter 6 LOOP FILTER WITH CAPACITANCE MULTIPLIER;141
9.1;6.1 Loop filter architecture;141
9.1.1;6.1.1 Passive loop filter;141
9.1.2;6.1.2 Dual-path loop filter;142
9.1.3;6.1.3 Sample-reset loop filter;145
9.1.4;6.1.4 Other loop filter architectures;147
9.1.5;6.1.5 Summary and comparison of loop filters;151
9.2;6.2 Loop filter and charge-pump noise mapping;152
9.3;6.3 Loop filter with capacitance multiplier;155
9.3.1;6.3.1 Third-order passive loop filter;155
9.3.2;6.3.2 Capacitance multiplier;156
9.3.3;6.3.3 Simulation of loop filter with capacitance multiplier;159
9.3.4;6.3.4 Noise consideration;162
9.4;REFERENCES;163
10;Chapter 7 OTHER BUILDING BLOCKS OF PLL;165
10.1;7.1 VCO;165
10.1.1;7.1.1 LC-VCO;165
10.1.2;7.1.2 Varactor;166
10.1.3;7.1.3 Inductor;169
10.1.4;7.1.4 VCO phase noise;170
10.1.5;7.1.5 Layout;175
10.2;7.2 Phase-frequency detector;176
10.3;7.3 Charge pump;178
10.3.1;7.3.1 Reference spur;178
10.3.2;7.3.2 Charge pump architectures;185
10.4;7.4 Programmable divider;187
10.5;7.5 Digital S. modulator;190
10.6;7.6 Chip layout;190
10.7;REFERENCES;192
11;Chapter 8 PROTOTYPE MEASUREMENT RESULTS;197
11.1;8.1 Prescaler measurement;197
11.2;8.2 Loop filter measurement;200
11.3;8.3 PLL measurement;202
11.4;REFERENCES;208
12;Chapter 9 CONCLUSIONS;209
13;APPENDIX --- Behavioral Modeling of Charge-pump PLL;212
14;Index;225