Chips and Intelligence

Low Power VLSI Design with Artificial Intelligence
1. Auflage 2026
ISBN: 978-1-041-17097-6
Verlag: Taylor & Francis Ltd

Buch, Englisch, 432 Seiten, Format (B × H): 156 mm x 234 mm

Reihe: Smart Engineering Systems: Design and Applications

The text provides a comprehensive and forward-looking exploration of the integration between low-power CMOS VLSI design and cutting-edge technologies such as artificial intelligence and machine learning.

- Explores how artificial intelligence techniques are revolutionizing VLSI design, focusing on optimizing low-power circuits and systems.

- Presents the latest advancements and research in both artificial intelligence and VLSI design, such as FinFET and nanosheet-based logic, analog integrated circuits design, and optimization with artificial intelligence.

- Offers perspectives on future trends and potential developments in the integration of artificial intelligence with VLSI design to reduce the complexity and time-consuming process of semiconductor IC design.

- Addresses techniques for achieving energy efficiency in both digital and analog components and presents future trends in low-power VLSI design.

- Discusses topics such as artificial intelligence-driven adaptive power management in VLSI design and neural networks in low-power VLSI architectures.

The text is primarily written for senior undergraduates, graduate students, and academic researchers in electrical engineering, electronics and communications engineering, microelectronics, VLSI design, artificial intelligence, computer science and engineering.

Zielgruppe

Academic, Postgraduate, and Undergraduate Advanced

Autoren/Hrsg.

Kandpal, Jyoti

Abhishek, Kumar

Pathak, Jyotirmoy

Dwivedi, Smrity

Tripathi, Suman Lata

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Halb- und Supraleitertechnologie
• Technische Wissenschaften Energietechnik | Elektrotechnik Elektrotechnik

Inhaltsverzeichnis

1. Foundations of Low-Power VLSI. 2. Introductions to Artificial Intelligence and Machine Learning. 3. Integration of Artificial Intelligence in Low-Power VLSI. 4. Artificial Intelligence-Optimized Power-Efficient VLSI Architectures. 5. Artificial Intelligence-Driven Adaptive Power Management in VLSI Design. 6. Approximate Computing Techniques on Machine Learning Architecture. 7. Neural Networks in Low-Power VLSI Architectures. 8. Artificial Intelligence-assisted Circuit Optimization. 9. Smart Memory Architectures. 10. Power-Aware Testing and Validation. 11. Neuromorphic Computing in Low-Power CMOS VLSI Circuits.

Über Autor(innen)

Abhishek Kumar is working as an associate professor in the School of Electronics and Electrical Engineering at Lovely Professional University, Punjab, India. With over eleven years of experience in academia, he has made significant contributions to research and education. His research output is impressive, comprising more than fifty-five research papers published in respected journals. Additionally, he has contributed to conference proceedings. His innovative work extends beyond publications; he has been actively involved in intellectual property creation, having published 20 patents and registered 5 copyrights. His areas of research interest include CMOS circuit design, hardware security, cryptanalysis, HDL-ASIC-FPGA, and machine learning.

Smrity Dwivedi is working as an Associate Professor in the Department of Electronics Engineering at the Indian Institute of Technology, BHU, Varanasi, India. He has more than ten years of academic and research experience. She has more than a hundred publications in international journals, IEEE transactions, international conferences, and national conferences. Her area of expertise is in conventional microwave tubes, high power microwave tubes, smart antenna design with metamaterial, graphene, siw, and biomedical applications with antenna.

Jyotirmoy Pathak works as an Assistant Professor in the School of Engineering and Technology at Christ University, Bangalore, India. Over twenty of his research papers have been published in Scopus/WoS-indexed journals and presented at IEEE/Springer conferences. His areas of research include side channel attack, VLSI design, low-power architecture, memory design, data converters, ASIC-SoC, and cryptology. Jyoti Kandpal is an Assistant Professor in the Department of Electronics and Communication Engineering at Graphic Era Hill University, Dehradun, India. Her research interests include digital VLSI, low-power VLSI design, and high-performance digital circuit design. She has published research papers in journals and conferences of national and international repute.

Suman Lata Tripathi is working as a Professor in the Department of Electronics and Telecommunications at Symbiosis International University, Pune, India. She has more than twenty-two years of experience in academics and research. She completed her remote post-doc from Nottingham Trent University, London, UK in the year 2022-23. She has published more than 135 research papers in journals, and conference proceedings. She has edited and authored more than 27 books in different areas of electronics and electrical engineering. She is associated as a senior member of IEEE, Fellow of IETE, and a Life member ISC. Her area of expertise includes microelectronics device modeling and characterization, low-power VLSI circuit design, VLSI design of testing, advanced FET design for IoT, Embedded System Design, reconfigurable architecture with FPGAs, and biomedical applications.