Top-Down Digital VLSI Design

From Architectures to Gate-Level Circuits and FPGAs
Erscheinungsjahr 2014
ISBN: 978-0-12-800730-3
Verlag: Elsevier Science

Buch, Englisch, 598 Seiten, Format (B × H): 189 mm x 233 mm, Gewicht: 1182 g

Top-Down VLSI Design: From Architectures to Gate-Level Circuits and FPGAs represents a unique approach to learning digital design. Developed from more than 20 years teaching circuit design, Doctor Kaeslin's approach follows the natural VLSI design flow and makes circuit design accessible for professionals with a background in systems engineering or digital signal processing. It begins with hardware architecture and promotes a system-level view, first considering the type of intended application and letting that guide your design choices.

Doctor Kaeslin presents modern considerations for handling circuit complexity, throughput, and energy efficiency while preserving functionality. The book focuses on application-specific integrated circuits (ASICs), which along with FPGAs are increasingly used to develop products with applications in telecommunications, IT security, biomedical, automotive, and computer vision industries. Topics include field-programmable logic, algorithms, verification, modeling hardware, synchronous clocking, and more.

Zielgruppe

<p>Students in upper undergraduate or graduate courses on studying VLSI and microelectronics, professional system engineers working in these areas</p>

Autoren/Hrsg.

Kaeslin, Hubert

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Schaltungsentwurf

Inhaltsverzeichnis

1. Introduction to Microelectronics 2. Field Programmable Logic 3. From Algorithms to Architectures 4. Circuit Modeling with Hardware Description Languages5. Functional Verification6. The Case for Synchronous Design7. Clocking of Synchronous Circuits 8. Acquisition of Asynchronous Data A. Elementary Digital Electronics B. Finite State Machines

Über Autor(innen)

Kaeslin, Hubert
Since 1989, Hubert Kaeslin has headed the Micro-electronics Design Center of ETH Zurich, which taped out more than 300 circuit designs under his supervision over the past 23 years, both for research and educational purposes. He has written more than 75 scientific papers and his professional interests extend to digital signal processing, IT security, graph theory, and visual formalisms. Dr. Kaeslin is a Senior Member of IEEE and has been awarded the title of professor by ETH in 2010.