Jha / Chen Nanoelectronic Circuit Design

1. Auflage 2010
ISBN: 978-1-4419-7609-3
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 485 Seiten

This book is about large-scale electronic circuits design driven by nanotechnology, where nanotechnology is broadly defined as building circuits using nanoscale devices that are either implemented with nanomaterials (e.g., nanotubes or nanowires) or following an unconventional method (e.g., FinFET or III/V compound-based devices). These nanoscale devices have significant potential to revolutionize the fabrication and integration of electronic systems and scale beyond the perceived scaling limitations of traditional CMOS. While innovations in nanotechnology originate at the individual device level, realizing the true impact of electronic systems demands that these device-level capabilities be translated into system-level benefits. This is the first book to focus on nanoscale circuits and their design issues, bridging the existing gap between nanodevice research and nanosystem design.

Autoren/Hrsg.

Chen, Deming

Jha, Niraj K.

Inhaltsverzeichnis

1;Nanoelectronic Circuit Design;3
1.1;Preface;5
1.2;Contents;7
1.3;Contributors;9
1.4;Introduction to Nanotechnology;13
1.4.1;1 FinFETs;15
1.4.2;2 Carbon Nanotube Devices;17
1.4.3;3 Graphene Nanoribbon Devices;21
1.4.4;4 Nanowire Devices;25
1.4.5;5 Resonant Tunneling Diodes and Quantum Cellular Automata;28
1.4.5.1;5.1 Resonant Tunneling Diodes;28
1.4.5.2;5.2 Quantum Cellular Automata;30
1.4.6;6 Conclusions;32
1.4.7;References;32
1.5;FinFET Circuit Design;35
1.5.1;1 Introduction;35
1.5.1.1;1.1 Shorted-Gate and Independent-Gate FinFETs;36
1.5.2;2 Logic Design Using SG/IG-Mode FinFETs;37
1.5.2.1;2.1 Design of Logic Gates;40
1.5.3;3 Threshold Voltage Control Through Multiple Supply Voltages for Power-Efficient FinFET Interconnects;41
1.5.3.1;3.1 The Principle of TCMS;43
1.5.3.2;3.2 Circuit Design Considerations;45
1.5.3.2.1;3.2.1 Power Consumption in TCMS Circuits;45
1.5.3.2.2;3.2.2 Exploratory Buffer Design for TCMS;45
1.5.3.3;3.3 Logic Design Using TCMS;46
1.5.4;4 Schmitt Trigger;49
1.5.5;5 Latch Design Using SG/IG-Mode FinFETs;51
1.5.5.1;5.1 SG-Mode Latch Design;51
1.5.5.2;5.2 IG-Mode FinFET Latch;52
1.5.6;6 Precharge-Evaluate Logic Circuits;53
1.5.6.1;6.1 FinFET Domino Logic Circuits with SG-Mode FinFETs;53
1.5.6.2;6.2 FinFET Domino Logic with IG-Mode FinFETs;55
1.5.7;7 FinFET Layout;56
1.5.7.1;7.1 Layout Analysis of FinFET Standard Cells (SG/IG-Mode);57
1.5.8;8 Oriented FinFETs;59
1.5.8.1;8.1 Library Design Using Oriented FinFETs;61
1.5.9;9 Conclusions;62
1.5.10;References;65
1.6;FinFET SRAM Design;67
1.6.1;1 Introduction to Nonplanar SRAM;67
1.6.2;2 Why FinFETs?;68
1.6.3;3 Physics, Theory, and Modeling of FinFET Devices for SRAM Applications;70
1.6.3.1;3.1 First-Order Poisson Equations;73
1.6.3.2;3.2 Sub-threshold Slope Tracking;73
1.6.3.3;3.3 Strong-Inversion Region Charge Tracking;74
1.6.4;4 SRAM Design;77
1.6.4.1;4.1 SRAM Design Requirements and Functionality Metrics;78
1.6.4.1.1;4.1.1 Metric 1: Read Stability;79
1.6.4.1.2;4.1.2 Metric 2: Writability;80
1.6.5;5 FinFET Design for SRAM;81
1.6.5.1;5.1 Example of FinFET Simulation Models Used for SRAM Design;81
1.6.5.2;5.2 3-D Thermal Modeling of FinFET;83
1.6.6;6 Low-Power, High-Performance 90-nm DG-FinFET SRAM Design;86
1.6.6.1;6.1 Design Overview;87
1.6.6.2;6.2 Device Models;87
1.6.6.3;6.3 Width Quantization;89
1.6.6.4;6.4 Layout and Surface Orientation: A Brief Overview;89
1.6.6.5;6.5 Performance;90
1.6.6.6;6.6 Power;92
1.6.6.7;6.7 Stability;92
1.6.7;7 A High Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology;93
1.6.7.1;7.1 Back-Gate Design Overview;93
1.6.7.2;7.2 Dynamic Bias Generator;95
1.6.7.3;7.3 Analysis of the FinFET SRAM;95
1.6.7.4;7.4 8T SRAM Cell;97
1.6.8;8 Low-Power and Stable FinFET SRAM;98
1.6.8.1;8.1 Design Overview;98
1.6.8.2;8.2 Leakage Current of Footer Device;100
1.6.9;9 Other Mixed Split/DG Designs;102
1.6.9.1;9.1 Column-Decoupled Design;103
1.6.9.1.1;9.1.1 8T-Decoupled Cell;103
1.6.9.1.2;9.1.2 6T-Decoupled Cell;103
1.6.10;References;106
1.7;A Hybrid Nano/CMOS Dynamically Reconfigurable System;108
1.7.1;1 Introduction;108
1.7.2;2 Background;111
1.7.2.1;2.1 NRAMs;111
1.7.2.2;2.2 MRAMs;112
1.7.2.3;2.3 PCMs;113
1.7.3;3 Temporal Logic Folding;114
1.7.4;4 Architecture of Nature;116
1.7.4.1;4.1 The SMB Architecture;117
1.7.4.2;4.2 Support for Reconfiguration;119
1.7.4.3;4.3 Parameter Optimization for the SMB Architecture;121
1.7.4.3.1;4.3.1 Number of LEs (n1) per MB;121
1.7.4.3.2;4.3.2 Number of MBs (n2) per SMB;122
1.7.4.3.3;4.3.3 Number of Inputs (m) per LUT;122
1.7.4.3.4;4.3.4 Number of Flip-flops (l) per LE;122
1.7.4.3.5;4.3.5 Number of Reconfiguration Sets (k);123
1.7.4.3.6;4.3.6 Different Types of Nano RAMs;124
1.7.4.4;4.4 Interconnect Design;124
1.7.5;5 Power Estimation;128
1.7.5.1;5.1 Switching Power Estimation;128
1.7.5.1.1;5.1.1 Effective Capacitance;129
1.7.5.1.2;5.1.2 Switching Activity;129
1.7.5.2;5.2 Leakage Power;131
1.7.6;6 Motivational Example for NanoMap;131
1.7.7;7 NanoMap: Overview of the Optimization Flow;133
1.7.8;8 Logic Mapping;135
1.7.8.1;8.1 Plane Separation;135
1.7.8.2;8.2 Folding Level Computation;136
1.7.8.2.1;8.2.1 Delay Minimization;138
1.7.8.2.1.1;Initial Folding Level Selection;138
1.7.8.2.1.2;Folding Level Adjustment;139
1.7.8.2.2;8.2.2 Area Minimization;139
1.7.8.2.2.1;Initial Folding Level Selection;140
1.7.8.2.2.2;Folding Level Adjustment;140
1.7.8.3;8.3 Module Library;140
1.7.8.4;8.4 RTL Module Partitioning;142
1.7.8.5;8.5 Force-Directed Scheduling;143
1.7.8.5.1;8.5.1 Creation of LUT Computation DG;143
1.7.8.5.2;8.5.2 Creation of Register Storage DG;144
1.7.8.5.3;8.5.3 Calculation of Forces;146
1.7.8.5.3.1;Self-Force;146
1.7.8.5.3.2;Predecessor and Successor Forces;148
1.7.8.5.4;8.5.4 Summary of the FDS Algorithm;149
1.7.9;9 Temporal Clustering;149
1.7.10;10 Temporal Placement and Routing;151
1.7.11;11 Simulation-Based Analysis;153
1.7.12;12 Conclusions;156
1.7.13;References;160
1.8;Reliable Circuits Design with Nanowire Arrays;163
1.8.1;1 Introduction;163
1.8.2;2 Fabrication Technologies;163
1.8.2.1;2.1 Nanowire Fabrication Techniques;164
1.8.2.1.1;2.1.1 Bottom-Up Techniques;164
1.8.2.1.2;2.1.2 Top-Down Techniques;164
1.8.2.2;2.2 Crossbar Technologies;165
1.8.2.2.1;2.2.1 Crossbars with Bottom-Up Nanowires;165
1.8.2.2.2;2.2.2 Nanomold-Based Nanowire Crossbars;166
1.8.2.2.3;2.2.3 Crossbar Switches;166
1.8.3;3 Architecture of Nanowire Crossbars;166
1.8.3.1;3.1 Organization of Nanowire Crossbars;166
1.8.3.2;3.2 Architectures Based on Nanowire Crossbars;167
1.8.3.3;3.3 Decoding Nanowires;168
1.8.3.3.1;3.3.1 Decoders for Differentiated Nanowires;169
1.8.3.3.2;3.3.2 Decoders for Undifferentiated Nanowires;169
1.8.4;4 Decoder Logic Design;170
1.8.4.1;4.1 Semantic of Multi-valued Logic Addressing;170
1.8.4.2;4.2 Code Construction;173
1.8.4.2.1;4.2.1 Hot Encoding;173
1.8.4.2.2;4.2.2 N-ary Reflexive Code;173
1.8.4.3;4.3 Defect Models;174
1.8.4.3.1;4.3.1 Basic Error Model;174
1.8.4.3.2;4.3.2 Overall Impact of Variability;175
1.8.4.4;4.4 Impact of the Encoding Scheme;177
1.8.5;5 Testing Crossbars;179
1.8.5.1;5.1 Testing Procedure;179
1.8.5.2;5.2 Perturbative Current Model;181
1.8.5.3;5.3 Stochastic Current Model;182
1.8.5.3.1;5.3.1 Distribution of the Useful Signal;183
1.8.5.3.2;5.3.2 Distribution of the Defect-Induced Noise;183
1.8.5.3.3;5.3.3 Distribution of the Intrinsic Noise;183
1.8.5.4;5.4 Test-Aware Design Optimization;184
1.8.5.5;5.5 Testing Procedure;186
1.8.5.6;5.6 Perturbative Current Model;187
1.8.5.7;5.7 Stochastic Current Model;189
1.8.5.7.1;5.7.1 Distribution of the Useful Signal;189
1.8.5.7.2;5.7.2 Distribution of Defect-Induced Noise;189
1.8.5.7.3;5.7.3 Distribution of the Intrinsic Noise;190
1.8.5.8;5.8 Test-Aware Design Optimization;190
1.8.6;6 Conclusions;192
1.8.7;Exercise 1Delay in a Crossbar;192
1.8.8;Exercise 2Process Optimization;193
1.8.9;References;194
1.9;Leveraging Emerging Technology Through Architectural Exploration for the Routing Fabric of Future FPGAs;1
1.9.1;1 Introduction;1
1.9.2;2 Primitives;1
1.9.2.1;2.1 Single-Walled Carbon Nanotube Bundled Interconnect;1
1.9.2.2;2.2 Nanowire-Based Crossbar Interconnect;1
1.9.3;3 Modeling of SWCNT Interconnect Bundles;1
1.9.4;4 Replacing Copper by SWCNT Bundle-Based Interconnect;1
1.9.4.1;4.1 Assumptions and Experimental Setup;1
1.9.4.2;4.2 Segmentation Experiments;1
1.9.4.3;4.3 SB/CB Configurations;1
1.9.5;5 Routing Fabric Design Using Crossbar and Molecular Switches;1
1.9.5.1;5.1 Architecture 1;1
1.9.5.2;5.2 Architecture 2;1
1.9.5.3;5.3 Evaluation;1
1.9.6;6 Results;1
1.9.7;7 Related Work;1
1.9.8;8 Conclusions;1
1.9.9;References;1
1.10;Nanoscale Application-Specific Integrated Circuits;223
1.10.1;1 Fabric Introduction;223
1.10.2;2 NASIC Building Blocks: Nanowires and xnwFETs;225
1.10.2.1;2.1 Semiconductor Nanowires;225
1.10.2.2;2.2 xnwFET Devices;226
1.10.2.2.1;2.2.1 Design Motivation and Nanowire-Level Approaches;227
1.10.2.2.2;2.2.2 xnwFET Device-Level Design Approaches;228
1.10.3;3 NASIC Circuit Styles;230
1.10.3.1;3.1 NASICs with Static Ratioed Logic;231
1.10.3.2;3.2 NASIC Dynamic Circuits and Timing Schemes;232
1.10.3.2.1;3.2.1 Sequential Circuits Using Dynamic Circuit Styles;234
1.10.3.3;3.3 Integrated Device-Circuit Exploration;236
1.10.3.3.1;3.3.1 Methodology;236
1.10.3.3.2;3.3.2 Control Schemes for the NASIC Fabric;240
1.10.4;4 NASIC Logic Styles;243
1.10.5;5 NASIC Architectures;244
1.10.5.1;5.1 Wire Streaming Processor;244
1.10.5.1.1;5.1.1 Wisp-0 Program Counter;244
1.10.5.1.2;5.1.2 Wisp-0 ALU;245
1.10.5.2;5.2 Nanodevice-Based Programmable Architectures;246
1.10.6;6 Built-in Fault Tolerance;248
1.10.6.1;6.1 Techniques for Masking Manufacturing Defects;249
1.10.6.1.1;6.1.1 Circuit-Level and Structural Redundancy;250
1.10.6.1.2;6.1.2 Interleaving Nanowires;251
1.10.6.1.3;6.1.3 Integrated Code-Based Error Masking;252
1.10.6.1.4;6.1.4 Voting at the Nanoscale;253
1.10.6.2;6.2 Density Evaluation;255
1.10.6.3;6.3 Yield Evaluation for WISP-0;257
1.10.6.4;6.4 Process Variation Mitigation;259
1.10.6.4.1;6.4.1 Initial Study on Impact of Redundancy for Masking Delay Faults;260
1.10.6.4.2;6.4.2 Design of Fast-Track Techniques;261
1.10.6.4.3;6.4.3 Method of Evaluation;262
1.10.6.4.4;6.4.4 Fast Track Results;264
1.10.7;7 Discussion on Performance and Power;266
1.10.8;8 Manufacturing;268
1.10.8.1;8.1 Fabric Choices Targeting Manufacturability;268
1.10.8.2;8.2 Manufacturing Pathway;269
1.10.8.2.1;8.2.1 Nanowire Growth and Alignment;271
1.10.8.2.2;8.2.2 Nanowire Grid Functionalization;275
1.10.9;9 Summary and Future Work;275
1.10.10;References;280
1.11;Imperfection-Immune Carbon Nanotube VLSI Circuits;284
1.11.1;1 Introduction;285
1.11.2;2 Mis-Positioned-CNT-Immune Logic Design;286
1.11.3;3 Metallic-CNT-Immune CNFET Circuits;295
1.11.3.1;3.1 ACCNT: Asymmetrically Correlated CNT Technology;295
1.11.3.2;3.2 VMR: VLSI-Compatible Metallic-CNT Removal;300
1.11.4;4 Probabilistic Analysis of CNFET Circuits;305
1.11.5;5 Conclusion;309
1.11.6;References;311
1.12;FPCNA: A Carbon Nanotube-Based Programmable Architecture;313
1.12.1;1 Introduction;314
1.12.2;2 Related Work;314
1.12.3;3 Design Flow;316
1.12.4;4 Nanoelectronic Devices;317
1.12.4.1;4.1 Carbon Nanotubes;317
1.12.4.2;4.2 CNT Field-Effect Transistors;319
1.12.4.3;4.3 CNT Logic;321
1.12.4.4;4.4 Nram;323
1.12.4.5;4.5 CNT-Bundle Interconnect;323
1.12.4.6;4.6 Solid-Electrolyte Nanoswitches;325
1.12.5;5 FPCNA Architecture;325
1.12.5.1;5.1 CNT-Based LUT;326
1.12.5.2;5.2 BLE Design;326
1.12.5.3;5.3 Logic Block Design;328
1.12.5.4;5.4 High-Level Architecture and Global Routing;330
1.12.6;6 Nanotube LUT Fabrication;332
1.12.7;7 Circuit Characterization;334
1.12.7.1;7.1 CNFET and CNT-Based LUT Variation;334
1.12.7.2;7.2 Crossbar Characterization;336
1.12.7.3;7.3 Timing Block Evaluation;336
1.12.8;8 CAD Flow;337
1.12.9;9 Experimental Results;342
1.12.9.1;9.1 Experimental Setup;342
1.12.9.2;9.2 Area Reduction;342
1.12.9.3;9.3 Performance Gain;344
1.12.10;10 Conclusion and Future Work;349
1.12.11;References;352
1.13;Graphene Transistors and Circuits;355
1.13.1;1 Introduction;355
1.13.2;2 Fabrication;356
1.13.2.1;2.1 Techniques to Open a Band-Gap;357
1.13.2.2;2.2 Graphene Transistors;360
1.13.3;3 Analog Circuits;362
1.13.4;4 Digital Circuits;365
1.13.4.1;4.1 GNRFET Digital Circuits;367
1.13.4.2;4.2 Ambipolar Logic Circuits;368
1.13.4.3;4.3 Tunneling FETs;369
1.13.5;5 Modeling and Simulation of Graphene Transistors;369
1.13.5.1;5.1 Charge-Collection Model;370
1.13.5.2;5.2 Quantum Simulation Techniques;372
1.13.5.3;5.3 Semi-classical Top-of-the-Barrier Modeling;373
1.13.5.4;5.4 Semi-classical Model with Tunneling;375
1.13.6;6 Conclusions and Prospects;377
1.13.7;References;378
1.14;Study of Performances of Low-k Cu, CNTs, and Optical Interconnects;383
1.14.1;1 Introduction;383
1.14.2;2 Circuit Parameter Modeling;384
1.14.2.1;2.1 Modeling Parameters for Copper;384
1.14.2.1.1;2.1.1 Conventional Interconnect Circuit and Its Performance Limit;387
1.14.2.1.2;2.1.2 Interconnect Application of Carbon Nanotubes;388
1.14.2.1.3;2.1.3 Modeling Parameters for SWCNT Bundles;389
1.14.2.1.4;2.1.4 Secondary Effect of SWCNT Resistance Contacts;394
1.14.2.1.5;2.1.5 Graphene Nanoribbon Interconnects;395
1.14.2.1.6;2.1.6 Optical Interconnects;396
1.14.3;3 Circuit Modeling;398
1.14.4;4 Local Interconnects: CNT Bundles Versus Cu;400
1.14.5;5 Global and Semiglobal Interconnects;402
1.14.5.1;5.1 Cu/CNT and Optical Global Wire Circuit Models;402
1.14.5.2;5.2 Latency and Energy per Bit as a Function of Scaling;403
1.14.5.3;5.3 Latency, Power Density and Bandwidth Density;406
1.14.5.4;5.4 Impact of CNT and Optics Technology Improvement;407
1.14.6;References;411
1.15;Circuit Design with Resonant Tunneling Diodes;414
1.15.1;1 Introduction;414
1.15.2;2 RTD Fundamentals;415
1.15.2.1;2.1 Bistable Logic Using RTDs;417
1.15.2.2;2.2 Noise Margins of RTD-HBT Threshold Logic Gates;419
1.15.2.3;2.3 Monostable-Bistable Logic Elements;422
1.15.2.4;2.4 Circuit Examples;426
1.15.3;3 Threshold Logic Synthesis for RTD-Based Devices;428
1.15.3.1;3.1 Theorems for Threshold Logic;430
1.15.3.2;3.2 Synthesis Methodology;432
1.15.3.3;3.3 An Example;437
1.15.4;4 Threshold Logic Testing for RTD-Based Devices;438
1.15.4.1;4.1 Fault Modeling;438
1.15.4.2;4.2 Irredundant Threshold Networks and Redundancy Removal;439
1.15.4.3;4.3 Test Generation;440
1.15.5;References;444
1.15.5.1;Online Educational Links;444
1.16;Circuit Design with Quantum Cellular Automata;445
1.16.1;1 Introduction;445
1.16.2;2 QCA Fundamentals;446
1.16.2.1;2.1 Basic Logic Gates and Interconnect;447
1.16.2.2;2.2 Clocking Scheme;449
1.16.3;3 Logic Design with QCA;451
1.16.3.1;3.1 Hand-Crafted Designs;451
1.16.3.2;3.2 QCA Logic Synthesis;455
1.16.3.3;3.3 Tile-Based QCA Design;461
1.16.4;4 Testing of QCA Circuits;463
1.16.5;5 CAD Tools for QCA Design;472
1.16.6;6 Fabrication Technology and Challenges;472
1.16.6.1;6.1 Metal-Dot QCA;472
1.16.6.2;6.2 Molelcular QCA;476
1.16.7;7 Future of QCA;479
1.16.8;8 Online Educational Links;480
1.16.9;References;481
1.17;Index;482