Jespers The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits
2010
ISBN: 978-0-387-47101-3
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark
The semi-empirical and compact model approaches
E-Book, Englisch, 171 Seiten, eBook
Reihe: Analog Circuits and Signal Processing
ISBN: 978-0-387-47101-3
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark
Zielgruppe
Professional/practitioner
Autoren/Hrsg.
Weitere Infos & Material
Preface. Notations. Chapter 1. Sizing the Intrinsic Gain Stage. Chapter 2. The Charge Sheet Model revisited. Chapter 3. Graphical interpretation of the Charge Sheet Model. Chapter 4. Compact modeling. Chapter 5. The real transistor. Chapter 6. The real Intrinsic Gain Stage. Chapter 7. The common gate configuration. Chapter 8. Sizing the Miller Op. Amp. Annex 1. How to utilize the C.D. ROM data. Annex 2. The MATLAB toolbox. Annex 3. Temperature and Mismatch, from C.S.M. to E.K.V. Annex 4. E.K.V. intrinsic capacitance models. Bibliography. Index.