Nanoscale Memory Repair

2011
ISBN: 978-1-4614-2794-0
Verlag: Springer

Buch, Englisch, 218 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 353 g

Reihe: Integrated Circuits and Systems

Yield and reliability of memories have degraded with device and voltage scaling in the nano-scale era, due to ever-increasing hard/soft errors and device parameter variations. This book systematically describes these yield and reliability issues in terms of mathematics and engineering, as well as an array of repair techniques, based on the authors’ long careers in developing memories and low-voltage CMOS circuits. Nanoscale Memory Repair gives a detailed explanation of the various yield models and calculations, as well as various, practical logic and circuits that are critical for higher yield and reliability.

Zielgruppe

Research

Autoren/Hrsg.

Itoh, Kiyoo

Horiguchi, Masashi

Fachgebiete

• Technische Wissenschaften Technik Allgemein Nanotechnologie
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Halb- und Supraleitertechnologie

Inhaltsverzeichnis

An Introduction to Repair Techniques: Basics of Redundancy.- Basics of Error Checking and Correction.- Comparison between Redundancy and ECC.- Repairs of Logic Circuits.- Redundancy: Models of Fault Distribution.- Yield Improvement through Redundancy.- Replacement Schemes.- Intra-Subarray Replacement.- Inter-Subarray Replacement.- Subarray Replacement.- Devices for Storing Addresses.- Testing for Redundancy.- Error Checking and Correction: Linear Algebra and Linear Codes.- Galois Field.- Error-Correcting Codes.- Coding and Decoding Circuits.- Theoretical Reduction in Soft-Error and Hard-Error Rates.- Application of ECC.- Testing for ECC.- Synergistic Effect of Redundancy and ECC: Repair of Bit Faults using Synergistic Effect.- Application of Synergistic Effect.