Customizable Embedded Processors

Design Technologies and Applications Volume .
Erscheinungsjahr 2006
ISBN: 978-0-12-369526-0
Verlag: Elsevier Science

Buch, Englisch, 528 Seiten, Format (B × H): 197 mm x 242 mm, Gewicht: 1050 g

Customizable processors have been described as the next natural step in the evolution of the microprocessor business: a step in the life of a new technology where top performance alone is no longer sufficient to guarantee market success. Other factors become fundamental, such as time to market, convenience, energy efficiency, and ease of customization. This book is the first to explore comprehensively one of the most fundamental trends which emerged in the last decade: to treat processors not as rigid, fixed entities, which designers include "as is� in their products; but rather, to build sound methodologies to tailor-fit processors to the specific needs of such products. This book addresses the goal of maintaining a very large family of processors, with a wide range of features, at a cost comparable to that of maintaining a single processor.

Zielgruppe

PRIMARY AUDIENCE: Engineers in industry working in embedded software, system architectures, processor architectures and design tools
SECONDARY AUDIENCE:
Academic researchers

Autoren/Hrsg.

Ienne, Paolo

Leupers, Rainer

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Mathematik | Informatik EDV | Informatik Technische Informatik Eingebettete Systeme
• Mathematik | Informatik EDV | Informatik Informatik Rechnerarchitektur
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Schaltungsentwurf

Inhaltsverzeichnis

Introduction
Business Opportunities: The Case of Wireless Applications
Logistic Challenges: Lofty Ambitions and Stark Realities of Customizing Processors
Architectural Description Languages
Retargetable Toolsets
Processor Configuration
Automatic Instruction-Set Extensions
Challenges to Automatic Customization
Toolset Support for Instruction-Set Extensions
Coprocessor Generation from Executable Code
Datapath Synthesis
Instruction Matching and Modelling
Processor Verification
Sub-RISC Processors
An ASIP for UMTS-FDD Cell Search
Hardware/software Trade-offs for Advanced 3G Channel Decoding
FPGA-Based Processor Implementation
Designing a H.264 Encoder with Real-World Tradeoffs